LF198JAN

www.ti.com

SNOSAJ2A – FEBRUARY 2005 – REVISED MARCH 2013

Electrical Characteristics DC Parameters (continued)

Symbol

Parameter

Sub-

Conditions

Notes

Min

Max

Unit

groups

Hold Capacitor Charge Current

-3.0

mA

1

-2.0

mA

2, 3

Hold Capacitor Charge Current

3.0

mA

1

2.0

mA

2, 3

Differential Logic Threshold

1.0

mA

1, 2, 3

Logic = 2.0V, Logic Ref = 2.0V

Differential Logic Threshold

-10

10

µA

1, 2, 3

Logic = 0.8V, Logic Ref = 2.0V

Hold Mode Leakage Current

-0.100

0.100

nA

1

-50

50

nA

2

Hold Mode Leakage Current

-0.100

0.100

nA

1

= 11.5V

-50

50

nA

2

Output Impedance

2.0

Ω

1, 2, 3

(HOLD) Step Voltage

-2.0

2.0

mV

1

= 11.5V

-5.0

5.0

mV

2, 3

-2.0

2.0

mV

1

= -11.5V

-5.0

5.0

mV

2, 3

Feedthrough Rejection Ratio

86

dB

1

80

dB

2, 3

86

dB

1

80

dB

2, 3

86

dB

1

80

dB

2, 3

86

dB

1

80

dB

2, 3

(1)

Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or

elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is ensured over full

input signal range.

(2)

Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an

additional 0.5 mV step with a 5V logic swing and a 0.01

μF hold capacitor. Magnitude of the hold step is inversely proportional to hold

capacitor value.

Copyright © 2005–2013, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Links: LF198JAN