SMBCLK

P

S

SMBDAT

P

S

LM95245

www.ti.com

SNIS148G – OCTOBER 2007 – REVISED MARCH 2013

SMBus Digital Switching Characteristics

The switching characteristics of the LM95245 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95245. They

adhere to, but are not necessarily, the SMBus specifications.

Unit

Parameter

Test Conditions

(Limit)

100

kHz (max)

SMBus Clock Frequency

10

kHz (min)

4.7

µs (min)

SMBus Clock Low Time

25

ms (max)

SMBus Clock High Time

4.0

µs (min)

SMBus Rise Time

(3)

1

µs (max)

SMBus Fall Time

(4)

0.3

µs (max)

Output Fall Time

250

ns (max)

(4)

SMBDAT and SMBCLK Time Low for Reset of

25

ms (min)

35

ms (max)

Data In Setup Time to SMBCLK High

250

ns (min)

300

ns (min)

Data Out Stable after SMBCLK Low

1075

ns (max)

Start Condition SMBDAT Low to SMBCLK Low

(Start condition hold before the first clock falling

100

ns (min)

edge)

Stop Condition SMBCLK High to SMBDAT Low

100

ns (min)

(Stop Condition Setup)

SMBus Repeated Start-Condition Setup Time,

0.6

µs (min)

SMBCLK High to SMBDAT Low

SMBus Free Time Between Stop and Start

1.3

µs (min)

Conditions

(1)

specifications are not guaranteed.

(2)

Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(3)

(4)

(5)

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

Figure 2. SMBus Communication

Copyright © 2007–2013, Texas Instruments Incorporated

Submit Documentation Feedback

7

Product Folder Links: LM95245