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MCF5275CVM166 bảng dữ liệu(PDF) 10 Page - Freescale Semiconductor, Inc

tên linh kiện MCF5275CVM166
Giải thích chi tiết về linh kiện  MCF5275 Integrated Microprocessor Family Hardware Specification
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MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
Design Recommendations
Freescale Semiconductor
10
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 2 shows situations in sequencing the I/O VDD (OVDD), SDRAM VDD (SDVDD), PLL VDD
(PLLVDD), and Core VDD (VDD).
Figure 2. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and OVDD is non-critical during power-up and power-down sequences.
SDVDD (2.5V or 3.3V) and OVDD are specified relative to VDD.
5.2.1.1
Power Up Sequence
If OVDD/SDVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads cause all pad
output drivers connected to the OVDD/SDVDD to be in a high impedance state. There is no limit on how
long after OVDD/SDVDD powers up before VDD must powered up. VDD should not lead the OVDD,
SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or high current will be in the internal ESD
protection diodes. The rise times on the power supplies should be slower than 1
μs to avoid turning on the
internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
1. Use 1
μs or slower rise time for all supplies.
2. VDD/PLLVDD and OVDD/SDVDD should track up to 0.9 V, then separate for the completion of
ramps with OVDD/SD VDD going to the higher external voltages. One way to accomplish this is to
use a low drop-out voltage regulator.
SDVDD (2.5V)
Supplies Stable
2
1
3.3V
2.5V
1.5V
0
Time
Notes:
VDD should not exceed OVDD, SDVDD or PLLVDD by more than
0.4 V at any time, including power-up.
Recommended that VDD should track OVDD/SDVDD/PLLVDD up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD, SDVDD,
VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
1.
2.
3.
4.
VDD,
OVDD, SDVDD, PLLVDD


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