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STM6710DWB6F bảng dữ liệu(PDF) 6 Page - STMicroelectronics |
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STM6710DWB6F bảng dữ liệu(HTML) 6 Page - STMicroelectronics |
6 / 21 page Description STM6700, STM6710 6/21 Doc ID 16887 Rev 2 Figure 1. Logic diagram 1. Open drain Figure 2. Pinout SOT23-6 1. Open drain Note: For the STM6700 and STM6710Q, pin 2 is a fixed VCC, thereby making it a triple voltage reset, while the STM6710 is a quad voltage reset. Table 2. Signal names Pin Name Type Function (STM6710 / STM6700) 1 V1IN Input Input voltage 1 2 V2IN Input/supply Input voltage 2 and device power supply pin VCC For the triple monitor voltage STM6700 and for STM6710Q, this pin is the VCC supply pin and it is not monitored 3 V3IN Input Input voltage 3 4 V4IN Input Input voltage 4 5 GND Supply Ground 6 RESET Output Active low, open drain RESET output. Output goes low when any input drops below the specified threshold. Once all inputs rise above their threshold voltages, RESET remains low for typical 200 ms (STM6710) before going high. For the triple monitor (STM6700) it remains low for 5 µs (propagation delay - no tREC). The open drain RESET has a weak (10 µA) internal pull-up to V2IN (STM6710) or VCC (STM6700/STM6710Q). V1IN V2IN / VCC STM6700 V4IN RESET (1) STM6710 AM04617v1 V3IN 1 V1IN V4IN V3IN V2IN (VCC) 2 3 4 6 SOT23-6 5 GND RESET (1) AM04618v1 STM6710 STM6700 |
Số phần tương tự - STM6710DWB6F |
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Mô tả tương tự - STM6710DWB6F |
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