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STM8S103F2 bảng dữ liệu(PDF) 4 Page - STMicroelectronics |
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4 / 117 page List of tables Table 1. STM8S103xx access line features .............................................................................................9 Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14 Table 3. TIM timer features ....................................................................................................................16 Table 4. Legend/abbreviations for pinout tables ...................................................................................19 Table 5. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................21 Table 6. STM8S103Fx pin description ...................................................................................................25 Table 7. I/O port hardware register map ................................................................................................29 Table 8. General hardware register map ...............................................................................................30 Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................40 Table 10. Interrupt mapping ...................................................................................................................42 Table 11. Option bytes .........................................................................................................................113 Table 12. Option byte description ...........................................................................................................44 Table 13. STM8S103K alternate function remapping bits for 32-pin devices ........................................46 Table 14. STM8S103F alternate function remapping bits for 20-pin devices ........................................47 Table 15. Unique ID registers (96 bits) .................................................................................................113 Table 16. Voltage characteristics ...........................................................................................................51 Table 17. Current characteristics ...........................................................................................................52 Table 18. Thermal characteristics ..........................................................................................................52 Table 19. General operating conditions .................................................................................................53 Table 20. Operating conditions at power-up/power-down ......................................................................54 Table 21. Total current consumption with code execution in run mode at VDD = 5 V .............................55 Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................56 Table 23. Total current consumption in wait mode at VDD = 5 V ............................................................57 Table 24. Total current consumption in wait mode at VDD = 3.3 V .........................................................57 Table 25. Total current consumption in active halt mode at VDD = 5 V ..................................................58 Table 26. Total current consumption in active halt mode at VDD = 3.3 V ...............................................59 Table 27. Total current consumption in halt mode at VDD = 5 V .............................................................60 Table 28. Total current consumption in halt mode at VDD = 3.3 V ..........................................................60 Table 29. Wakeup times .........................................................................................................................60 Table 30. Total current consumption and timing in forced reset state ....................................................61 Table 31. Peripheral current consumption .............................................................................................62 Table 32. HSE user external clock characteristics .................................................................................65 Table 33. HSE oscillator characteristics .................................................................................................66 Table 34. HSI oscillator characteristics ..................................................................................................67 Table 35. LSI oscillator characteristics ...................................................................................................69 Table 36. RAM and hardware registers ..................................................................................................70 Table 37. Flash program memory/data EEPROM memory ....................................................................70 Table 38. I/O static characteristics .........................................................................................................71 Table 39. Output driving current (standard ports) ..................................................................................73 Table 40. Output driving current (true open drain ports) ........................................................................74 Table 41. Output driving current (high sink ports) ..................................................................................74 Table 42. NRST pin characteristics ........................................................................................................79 Table 43. SPI characteristics ..................................................................................................................82 Table 44. I 2C characteristics ..................................................................................................................85 Table 45. ADC characteristics ................................................................................................................87 Table 46. ADC accuracy with RAIN < 10 kΩ , VDD= 5 V .........................................................................87 Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V ..............................................................88 DocID15441 Rev 9 4/117 STM8S103K3 STM8S103F3 STM8S103F2 List of tables |
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