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STM8S005K6T6TR bảng dữ liệu(PDF) 6 Page - STMicroelectronics

tên linh kiện STM8S005K6T6TR
Giải thích chi tiết về linh kiện  Value line, 16 MHz STM8S 8-bit MCU, 32 Kbytes Flash, data EEPROM,10-bit ADC, timers, UART, SPI, I짼C
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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List of figures
Figure 1. STM8S005xx value line block diagram .....................................................................................9
Figure 2. Flash memory organization ....................................................................................................12
Figure 3. LQFP 48-pin pinout .................................................................................................................20
Figure 4. LQFP 32-pin pinout
................................................................................................................21
Figure 5. Memory map ...........................................................................................................................25
Figure 6. Supply current measurement conditions ................................................................................49
Figure 7. Pin loading conditions .............................................................................................................50
Figure 8. Pin input voltage .....................................................................................................................50
Figure 9. fCPUmax versus VDD ................................................................................................................54
Figure 10. External capacitor CEXT .......................................................................................................55
Figure 11. Typ. IDD(RUN) vs. VDD , HSE user external clock, fCPU = 16 MHz ...........................................64
Figure 12. Typ. IDD(RUN) vs. fCPU , HSE user external clock, VDD= 5 V ..................................................64
Figure 13. Typ. IDD(RUN) vs. VDD , HSI RC osc, fCPU = 16 MHz ..............................................................65
Figure 14. Typ. IDD(WFI) vs. VDD , HSE user external clock, fCPU = 16 MHz ............................................65
Figure 15. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V ....................................................65
Figure 16. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz ................................................................66
Figure 17. HSE external clocksource .....................................................................................................67
Figure 18. HSE oscillator circuit diagram ...............................................................................................68
Figure 19. Typical HSI frequency variation vs VDD @ 3 temperatures ..................................................69
Figure 20. Typical LSI frequency variation vs VDD @ 3 temperatures ...................................................70
Figure 21. Typical VIL and VIH vs VDD @ 3 temperatures ......................................................................73
Figure 22. Typical pull-up resistance vs VDD @ 3 temperatures ............................................................73
Figure 23. Typical pull-up current vs VDD @ 3 temperatures .................................................................73
Figure 24. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................75
Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................76
Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................76
Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................76
Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................77
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................77
Figure 30. Typ. VDD - VOH @ VDD = 5 V (standard ports) .......................................................................77
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ....................................................................78
Figure 32. Typ. VDD - VOH @ VDD = 5 V (high sink ports) ......................................................................78
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) ...................................................................78
Figure 34. Typical NRST VIL and VIH vs VDD @ 3 temperatures ...........................................................80
Figure 35. Typical NRST pull-up resistance vs VDD @ 3 temperatures .................................................80
Figure 36. Typical NRST pull-up current vs VDD @ 3 temperatures ......................................................80
Figure 37. Recommended reset pin protection ......................................................................................81
Figure 38. SPI timing diagram - slave mode and CPHA = 0 ..................................................................83
Figure 39. SPI timing diagram - slave mode and CPHA = 1
(1)
.............................................................83
Figure 40. SPI timing diagram - master mode
(1)
...................................................................................84
Figure 41. Typical application with I
2C bus and timing diagram (1) .......................................................85
Figure 42. ADC accuracy characteristics ...............................................................................................89
Figure 43. Typical application with ADC ................................................................................................89
Figure 44. 48-pin low profile quad flat package (7 x 7) ..........................................................................93
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................95
Figure 46. STM8S005xx value line ordering information scheme .........................................................99
DocID022186 Rev 3
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STM8S005K6 STM8S005C6
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