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4 / 22 page 74VHC_VHCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 4 July 2012 4 of 22 NXP Semiconductors 74VHC595; 74VHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 6. Pinning information 6.1 Pinning 6.2 Pin description (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 74VHC595 74VHCT595 Q1 VCC Q2 Q0 Q3 DS Q4 OE Q5 STCP Q6 SHCP Q7 MR GND Q7S 001aak048 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 001aak049 74VHC595 74VHCT595 Q7 MR Q6 SHCP Q5 STCP Q4 OE Q3 DS Q2 Q0 Transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 terminal 1 index area GND(1) Table 2. Pin description Symbol Pin Description Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input Q0 15 parallel data output 0 VCC 16 supply voltage |
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