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STM8L152M8 bảng dữ liệu(PDF) 7 Page - STMicroelectronics |
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STM8L152M8 bảng dữ liệu(HTML) 7 Page - STMicroelectronics |
7 / 134 page DocID17943 Rev 6 7/134 STM8L15xx8, STM8L15xR6 List of figures 8 List of figures Figure 1. High density and medium+ density STM8L15xx device block diagram . . . . . . . . . . . . . . 13 Figure 2. Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 3. STM8L151M8 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 4. STM8L152M8 80-pin package pinout (with LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5. STM8L151R8 and STM8L151R6 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . 26 Figure 6. STM8L152R8 and STM8L152R6 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7. STM8L151C8 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 8. STM8L152C8 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 12. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 13. Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz . . . . . . . . . . . . . . 75 Figure 14. Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz . . . . . . . . . . . . . 75 Figure 15. Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz . . . . . . . . . . . . . . 78 Figure 16. Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . 78 Figure 17. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 80 Figure 18. Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . 82 Figure 19. Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 20. Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 21. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 22. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 23. Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 24. Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 25. Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 26. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 27. Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 28. Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 29. Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 30. Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 31. Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 32. Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 33. Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 34. Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 35. Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 36. Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 37. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 38. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 39. SPI1 timing diagram - slave mode and CPHA=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 40. SPI1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 41. Typical application with I2C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 42. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 43. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 44. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 45. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 118 Figure 46. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 118 Figure 47. LQFP80, 14 x 14 mm, 80-pin low profile quad flat package . . . . . . . . . . . . . . . . . . . . . . . 123 |
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