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ADS5287IRGCR bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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ADS5287IRGCR bảng dữ liệu(HTML) 3 Page - Texas Instruments |
3 / 42 page ADS5287 www.ti.com SBAS428D – JANUARY 2008 – REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS ADS5287 PARAMETER MIN TYP MAX UNIT SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES AVDD Analog supply voltage 3.0 3.3 3.6 V LVDD Digital supply voltage 1.7 1.8 1.9 V Differential input voltage range 2 VPP Input common-mode voltage VCM ± 0.05 V REFT External reference mode 2.5 V REFB External reference mode 0.5 V CLOCK INPUTS ADCLK input sample rate 1/ tC 10 50, 65 MSPS Input clock amplitude differential (VCLKP–VCLKN) peak-to-peak Sine wave, ac-coupled 3.0 VPP LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Input clock CMOS, single-ended (VCLKP) VIL 0.6 V VIH 2.2 V Input clock duty cycle 50 % DIGITAL OUTPUTS ADCLKP and ADCLKN outputs (LVDS) 10 1x (sample rate) 50, 65 MHz LCLKP and LCLKN outputs (LVDS) 60 6x (sample rate) 300, 390 MHz CLOAD Maximum external capacitance from each pin to LVSS 5 pF RLOAD Differential load resistance between the LVDS output pairs 100 Ω TA Operating free-air temperature –40 +85 °C INITIALIZATION REGISTERS If the analog input is ac-coupled, the following registers must be written to in the order listed below. ADDRESS (hex) DATA (hex) Initialization Register 1 01 0010 Initialization Register 5 E2 00C0 To disable the PLL configuration switching (especially useful in systems where a system-level timing calibration is done once after power-up), the following registers must be written to in the order listed below. Also, see section PLL Operation Across Sampling Frequency. ADDRESS (hex) DATA (hex) For 10 ≤ Fs ≤ 25 (1) E3 0060 For 15 ≤ Fs = ≤ 45 (1) E3 00A0 (1) where Fs = sampling clock frequency Copyright © 2008–2012, Texas Instruments Incorporated 3 |
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