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ADP3308ART-2.5 bảng dữ liệu(PDF) 6 Page - Analog Devices |
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ADP3308ART-2.5 bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 8 page ADP3308 –6– REV. B THEORY OF OPERATION The new anyCAP LDO ADP3308 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider consisting of R1 and R2, which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. gm ADP3308 PTAT VOS NONINVERTING WIDEBAND DRIVER INPUT OUTPUT COMPENSATION CAPACITOR ATTENUATION (VBANDGAP/VOUT) R3 D1 R1 Q1 PTAT CURRENT R2 (a) RLOAD CLOAD GND R4 Figure 2. Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The temperature proportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibil- ity on the tradeoff of noise sources that leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a tempera- ture stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resis- tance. Moreover, the ESR value required to keep conventional LDOs stable, changes, depending on load and temperature. These ESR limitations make designing with LDOs more diffi- cult because of their unclear specifications and extreme varia- tions over temperature. This is no longer true with the ADP3308 anyCAP LDO. It can be used with virtually any capacitor, with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 0.47 µF capacitor on the output. Addi- tional advantages of the design scheme include superior line noise rejection and very high regulator gain which leads to excellent line and load regulation. An impressive ±2.2% accuracy is guar- anteed over line, load and temperature. Additional features of the circuit include current limit and ther- mal shutdown. Compared to the standard solutions that give warning after the output has lost regulation, the ADP3308 pro- vides improved system performance by enabling the ERR pin to give warning before the device loses regulation. As the chip’s temperature rises above 165 °C, the circuit activates a soft thermal shutdown, indicated by a signal low on the ERR pin, to reduce the current to a safe level. APPLICATION INFORMATION Capacitor Selection: anyCAP Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3308 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is needed for stability. However, larger capacitors can be used if high output current surges are anticipated. The ADP3308 is stable with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Input Bypass Capacitor: an input bypass capacitor is not required. However, for applications where the input source is high imped- ance or far from the input pin, a bypass capacitor is recommended. Connecting a 0.47 µF capacitor from the input pin (Pin 1) to ground reduces the circuit’s sensitivity to PC board layout. If a bigger output capacitor is used, the input capacitor must be 1 µF minimum. Thermal Overload Protection The ADP3308 is protected against damage due to excessive power dissipation by its thermal overload protection circuit which limits the die temperature to a maximum of 165 °C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165 °C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 125 °C. Calculating Junction Temperature Device power dissipation is calculated as follows: PD = (VIN – VOUT) ILOAD + (VIN) IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. Assuming ILOAD = 50 mA, IGND = 2 mA, VIN = 5.5 V and VOUT = 2.7 V, device power dissipation is: PD = (5.5 – 2.7) 50 mA + 5.5 × 2 mA = 151 mW ∆T = TJ – TA = PD × θJA = 151 × 165 = 24.9°C With a maximum junction temperature of 125 °C, this yields a maximum ambient temperature of ~100 °C. Printed Circuit Board Layout Consideration Surface mount components rely on the conductive traces or pads to transfer heat away from the device. Appropriate PC board layout techniques should be used to remove heat from the immediate vicinity of the package. |
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