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ADP3302 bảng dữ liệu(PDF) 6 Page - Analog Devices |
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ADP3302 bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 8 page ADP3301 –6– REV. 0 APPLICATION INFORMATION anyCAP™* The ADP3301 is very easy to use. The only external component required for stability is a small 0.47 µF bypass capacitor on the output. Unlike the conventional LDO designs, the ADP3301 is stable with virtually any type of capacitors (anyCAP™*) indepen- dent of the capacitor’s ESR (Effective Series Resistance) value. In a typical application, if the shutdown feature is not used, the shutdown pin (Pin 5) should be tied to the input pin. Pins 7 and 8 must be tied together, as well as Pins 1 and 2, for proper operation. Capacitor Selection Output Capacitors: as with any micropower device, output transient response is a function of the output capacitance. The ADP3301 is stable with a wide range of capacitor values, types and ESR (anyCAP™*). A capacitor as low as 0.47 µF is all that is needed for stability. However, larger capacitors can be used if high output current surges are anticipated. The ADP3301 is stable with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Input Bypass Capacitor: an input bypass capacitor is not required; however, for applications where the input source is high impedance or far from the input pins, a bypass capacitor is recommended. Connecting a 0.47 µF capacitor from the input pins (Pins 7 and 8) to ground reduces the circuit’s sensitivity to PC board layout. If a bigger output capacitor is used, the input capacitor should be 1 µF minimum. Low ESR capacitors offer better performance on a noisy supply; however, for less demanding requirements a standard tantalum or aluminum electrolythic capacitor is adequate. Noise Reduction A noise reduction capacitor (CNR) can be used to further reduce the noise by 6 dB–10 dB (Figure 20). Low leakage capacitors in the 10 nF–100 nF range provide the best performance. Since the noise reduction pin (NR) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible. Long PC board traces are not recommended. IN OUT ERR GND ADP3301-5.0 NR + 6 7 8 1 2 3 4 5 ON OFF + SD CNR 10nF C2 10µF R1 330k Ω EOUT C1 1µF VOUT = 5V VIN Figure 20. Noise Reduction Circuit Thermal Overload Protection The ADP3301 is protected against damage due to excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165 °C. Under extreme conditions (i.e., high ambient temperature and high power dissipation) where die temperature starts to rise above 165 °C, the output current is reduced until die tempera- ture has dropped to a safe level. Output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 125 °C. Calculating Junction Temperature Device power dissipation is calculated as follows : PD = (VIN – VOUT) ILOAD + (VIN) IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are input and output voltages respectively. Assuming ILOAD = 100 mA, IGND = 2 mA, VIN = 9 V and VOUT = 5.0 V, device power dissipation is: PD = (9 V – 5 V) 100 mA + (9 V) 2 mA = 418 mW The proprietary package used in ADP3301 has a thermal resistance of 96 °C/W, significantly lower than a standard 8-pin SOIC package at 170 °C/W. Junction temperature above ambient temperature will be approximately equal to : 0.418 W × 96°C/W = 40.1°C To limit the maximum junction temperature to 125 °C, maxi- mum ambient temperature must be lower than: TA(MAX) = 125 °C – 40.1°C = 84.9°C Printed Circuit Board Layout Consideration All surface mount packages rely on the traces of the PC board to conduct heat away from the package. In standard packages the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. In typical thermally enhanced packages, one or more of the leads are fused to the die attach pad, significantly decreasing this component. However, to make the improvement meaningful, a significant copper area on the PCB has to be attached to these fused pins. The ADP3301’s patented thermal coastline lead frame design uniformly minimizes the value of the dominant portion of the thermal resistance. It ensures that heat is conducted away by all pins of the package. This yields a very low 96 °C/W thermal resistance for an SO-8 package, without any special board layout requirements, relying on the normal traces connected to the leads. The thermal resistance can be decreased by approxi- mately an additional 10% by attaching a few square cm of copper area to the VIN pin of the ADP3301 package. |
Số phần tương tự - ADP3302 |
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Mô tả tương tự - ADP3302 |
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