ADM697AQ datasheet(2/12 Pages) AD

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ADM696/ADM697–SPECIFICATIONS

Parameter

Min

Typ

Max

Units

Test Conditions/Comments

VCC Operating Voltage Range

3.0

5.5

V

VBATT Operating Voltage Range

2.0

VCC – 0 3

V

BATTERY BACKUP SWITCHING (ADM696)

VOUT Output Voltage

VCC – 0.05

VCC – 0.025

V

IOUT = 1 mA

VCC – 0.5

VCC – 0.25

V

IOUT ≤ 100 mA

VOUT in Battery Backup Mode

VBATT – 0.05

VBATT – 0.02

V

IOUT = 250 µA, VCC < VBATT – 0.2 V

Supply Current (Excludes IOUT)

1

1.95

mA

IOUT = 100 mA

Supply Current in Battery Backup Mode

0.6

1

µAV

CC = 0 V, VBATT = 2.8 V

Battery Standby Current

5.5 V > VCC > VBATT + 0.2 V

(+ = Discharge, – = Charge)

–0.1

+0.02

µAT

A = +25°C

–1

+0.02

µA

Battery Switchover Threshold

70

mV

Power-Up

VCC – VBATT

50

mV

Power-Down

Battery Switchover Hysteresis

20

mV

BATT ON Output Voltage

0.4

V

ISINK = 1.6 mA

BATT ON Output Short Circuit Current

7

mA

BATT ON = VOUT = 2.4 V Sink Current

0.5

1

25

µA

BATT ON = VOUT, VCC = 0 V, Source Current

RESET AND WATCHDOG TIMER

Low Line Threshold (LLIN)

1.25

1.3

1.35

V

VCC = +5 V, +3 V

Reset Timeout Delay

35

50

70

ms

OSC SEL = HIGH, VCC= 5 V, TA = +25°C

Watchdog Timeout Period, Internal Oscillator

1.0

1.6

2.25

s

Long Period, VCC = 5 V, TA = +25

°C

70

100

140

ms

Short Period, VCC = 5 V, TA = +25°C

Watchdog Timeout Period, External Clock

4032

4097

Cycles

Long Period

960

1025

Cycles

Short Period

Minimum WDI Input Pulse Width

50

ns

VIL = 0.4, VIH = 3.5 V, VCC = 5 V

RESET

Output Voltage @ VCC = +1 V

4

200

mV

ISINK = 10

µA, V

CC = 1 V

RESET, RESET Output Voltage

0.4

V

ISINK = 400 µA, VCC = 2 V, VBATT = 0 V

0.4

V

ISINK = 1.6 mA, 3 V < VCC < 5.5 V

3.5

V

ISOURCE = 1 µA, VCC = 5 V

LOW LINE

, WDO Output Voltage

0.4

V

ISINK = 1.6 mA,

3.5

V

ISOURCE = 1

µA, V

CC = 5 V

Output Short Circuit Source Current

1

3

25

µA

WDI Input Threshold

VCC = 5 V

1

Logic Low

0.8

V

Logic High

3.5

V

WDI Input Current

20

50

µA

WD1 = VOUT, (VCC) TA = +25°C

–50

–15

µA

WD1 = 0 V, TA = +25°C

POWER FAIL DETECTOR

PFI Input Threshold

1.2

1.3

1.4

V

VCC = +3 V, +5 V

PFI–LLIN Threshold Difference

–50

±15

+50

mV

VCC = +3 V, +5 V

PFI Input Current

–25

±0.01

+25

nA

LLIN Input Current

–50

±0.01

+50

nA

PFO

Output Voltage

0.4

V

ISINK = 1.6 mA

3.5

V

ISOURCE = 1 µA, VCC = 5 V

PFO

Short Circuit Source Current

1

3

25

µA

PFI = Low, PFO = 0 V

CHIP ENABLE GATING (ADM697)

CEIN Threshold

0.8

V

VIL

3.0

V

VIH, VCC = 5 V

CEIN Pullup Current

3

µA

CEOUT Output Voltage

0.4

V

ISINK = 1.6 mA

VCC – 0.5

V

ISOURCE = 800 µA

CE

Propagation Delay

5

25

ns

OSCILLATOR

OSC IN Input Current

±2

µA

OSC SEL Input Pullup Current

5

µA

OSC IN Frequency Range

0

250

kHz

OSC SEL = 0 V

OSC IN Frequency with Ext. Capacitor

4

kHz

OSC SEL = 0 V, COSC = 47 pF

NOTE

1WDI is a three-level input which is internally biased to 38% of V

CC and has an input impedance of approximately 125 k

Ω.

Specifications subject to change without notice.

REV. 0

–2–

(VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to TMAX

unless otherwise noted.)

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