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ADM1062ASUZ bảng dữ liệu(PDF) 7 Page - Analog Devices |
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ADM1062ASUZ bảng dữ liệu(HTML) 7 Page - Analog Devices |
7 / 36 page ADM1062 Rev. C | Page 7 of 36 Parameter Min Typ Max Unit Test Conditions/Comments IOL3 20 mA Maximum sink current per PDOx pin ISINK3 60 mA Maximum total sink for all PDOx pins RPULL-UP 16 20 29 kΩ Internal pull-up ISOURCE (VPx)3 2 mA Current load on any VPx pull-ups, that is, total source current available through any number of PDOx pull-up switches configured onto any one VPx pin Three-State Output Leakage Current 10 μA VPDO = 14.4 V Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock DIGITAL INPUTS (VXx, A0, A1) Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V Input High Current, IIH −1 μA VIN = 5.5 V Input Low Current, IIL 1 μA VIN = 0 V Input Capacitance 5 pF Programmable Pull-Down Current, IPULL-DOWN 20 μA VDDCAP = 4.75 V TA = 25°C if known logic state is required SERIAL BUS DIGITAL INPUTS (SDA, SCL) Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Output Low Voltage, VOL3 0.4 V IOUT = −3.0 mA SERIAL BUS TIMING4 Clock Frequency, fSCLK 400 kHz Bus Free Time, tBUF 1.3 μs Start Setup Time, tSU;STA 0.6 μs Stop Setup Time, tSU;STO 0.6 μs Start Hold Time, tHD;STA 0.6 μs SCL Low Time, tLOW 1.3 μs SCL High Time, tHIGH 0.6 μs SCL, SDA Rise Time, tR 300 ns SCL, SDA Fall Time, tF 300 ns Data Setup Time, tSU;DAT 100 ns Data Hold Time, tHD;DAT 5 ns Input Low Current, IIL 1 μA VIN = 0 V SEQUENCING ENGINE TIMING State Change Time 10 μs 1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP. 2 All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured. 3 Specification is not production tested but is supported by characterization data at initial product release. 4 Timing specifications are guaranteed by design and supported by characterization data. |
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