công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADS8320E2K5G4 bảng dữ liệu(PDF) 10 Page - Texas Instruments |
|
ADS8320E2K5G4 bảng dữ liệu(HTML) 10 Page - Texas Instruments |
10 / 21 page ADS8320 10 SBAS108D www.ti.com SYMBOL DESCRIPTION MIN TYP MAX UNITS tSMPL Analog Input Sample Time 4.5 5.0 Clk Cycles tCONV Conversion Time 16 Clk Cycles tCYC Throughput Rate 100 kHz tCSD CS Falling to 0 ns DCLOCK LOW tSUCS CS Falling to 20 ns DCLOCK Rising thDO DCLOCK Falling to 5 15 ns Current DOUT Not Valid tdDO DCLOCK Falling to Next 30 50 ns DOUT Valid tdis CS Rising to DOUT Tri-State 70 100 ns ten DCLOCK Falling to DOUT 20 50 ns Enabled tf DOUT Fall Time 5 25 ns tr DOUT Rise Time 7 25 ns FIGURE 3. ADS8320 Basic Timing Diagrams. TABLE I. Timing Specifications (VCC = 2.7V and above, –40 °C to +85°C. DESCRIPTION ANALOG VALUE Full-Scale Range VREF Least Significant VREF/65,536 Bit (LSB) BINARY CODE HEX CODE Full-Scale VREF – 1 LSB 1111 1111 1111 1111 FFFF Midscale VREF/2 1000 0000 0000 0000 8000 Midscale – 1LSB VREF/2 – 1 LSB 0111 1111 1111 1111 7FFF Zero 0V 0000 0000 0000 0000 0000 DIGITAL OUTPUT STRAIGHT BINARY TABLE II. Ideal Input Voltages and Output Codes. SERIAL INTERFACE The ADS8320 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as shown in Figure 3 and Table I. The DCLOCK signal syn- chronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. How- ever, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and outputs a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT outputs the conversion result, most significant bit first. After the least significant bit (B0) has been output, subse- quent clocks repeat the output data but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. DATA FORMAT The output data from the ADS8320 is in Straight Binary format, as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. POWER DISSIPATION The architecture of the converter, the semiconductor fabrica- tion process, and a careful design allow the ADS8320 to convert at up to a 100kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8320 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the requirements of the system. In addition, the ADS8320 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (as shown in Figure 3). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very impor- tant as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continu- ously, until the power-down mode is entered. CS/SHDN D OUT DCLOCK Complete Cycle Power Down Conversion Sample Use positive clock edge for data transfer t SUCS t CONV t SMPL NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. B15 (MSB) B14 B13 B12 B11 B10 B9 B8 B0 (LSB) B7 B1 B6 B2 B5 B3 B4 Hi-Z 0 Hi-Z t CSD |
Số phần tương tự - ADS8320E2K5G4 |
|
Mô tả tương tự - ADS8320E2K5G4 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |