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ADS7835 bảng dữ liệu(PDF) 8 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  12-Bit, High-Speed, Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
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ADS7835
®
EXTERNAL REFERENCE
The internal reference is connected to the VREF pin and to the
internal buffer via a 10k
Ω series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.3V
to 2.9V, corresponding to an analog input range of 2.3V to
2.9V in both cases.
While the external reference will not source significant
current into the VREF pin, it does have to drive the 10kΩ
series resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
±30% from part to part). In addition, the V
REF pin should
still be bypassed to ground with at least a 0.1
µF ceramic
capacitor (placed as close to the ADS7835 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2
µF tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. The other is to provide greater
stability over temperature. (The internal reference is typi-
cally 20ppm/
°C which translates into a full-scale drift of
roughly one output code for every 12
°C. This does not take
into account other sources of full-scale drift.) If greater
stability over temperature is needed, then an external refer-
ence with lower temperature drift will be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7835. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (tCKCH and tCKCS). However, if these times
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high imped-
ance and goes LOW, the conversion has started and that
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
Acquisition Time
350
ns
tCONV
Conversion Time
1.625
µs
tCKP
Clock Period
125
5000
ns
tCKL
Clock LOW
50
ns
tCKH
Clock HIGH
50
ns
tCKDH
Clock Falling to Current Data
5
15
ns
Bit No Longer Valid
tCKDS
Clock Falling to Next Data Valid
30
50
ns
tCVL
CONV LOW
40
ns
tCVH
CONV HIGH
40
ns
tCKCH
CONV Hold after Clock Falls(1)
10
ns
tCKCS
CONV Setup to Clock Falling(1)
10
ns
tCKDE
Clock Falling to DATA Enabled
20
50
ns
tCKDD
Clock Falling to DATA
70
100
ns
High Impedance
tCKSP
Clock Falling to Sample Mode
5
ns
tCKPD
Clock Falling to Power-Down Mode
50
ns
tCVHD
CONV Falling to Hold Mode
5
ns
(Aperture Delay)
tCVSP
CONV Rising to Sample Mode
5
ns
tCVPU
CONV Rising to Full Power-up
50
ns
tCVDD
CONV Changing State to DATA
70
100
ns
High Impedance
tCVPD
CONV Changing State to
50
ns
Power-Down Mode
tDRP
CONV Falling to Start of CLK
5
µs
(for hold droop < 0.1 LSB)
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (TA = –40°C to +85°C,
CLOAD = 30pF).
FIGURE 2. Serial Data and Clock Timing.
DATA
CLK
t
CKH
t
CKP
t
CKDH
t
CKDS
t
CKL


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