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MC34932 bảng dữ liệu(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC34932 bảng dữ liệu(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 24 page  Analog Integrated Circuit Device Data Freescale Semiconductor 11 34932 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34932 has two identical H-Bridge drivers in the same package. The only connection shared internally is the Analog Ground (AGND). This description is given for the H-Bridge A half of the total device. However, the H-Bridge B half exhibits identical behavior. Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make the 34932 a very attractive, cost- effective solution for controlling a broad range of small DC motors. The 34932 outputs are capable of supporting peak DC load currents of up to 5.0 A from a 28 V VPWR source. An internal charge pump and gate drive circuitry are provided which can support external PWM frequencies up to 11 kHz. The 34932 has an analog feedback (current mirror) output pin (the FB pin) which provides a constant-current source ratioed to the active high side MOSFETs’ current. This can be used to provide monitoring of output current to facilitate closed-loop operation for motor speed/torque control, or for the detection of open load conditions. Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. Two independent disable inputs, D1 and EN/D2, provide the means to force the H-bridge outputs to a high-impedance state (all H-bridge switches OFF). The EN/D2 pin also controls an enable function allowing the IC to be placed in a power-conserving Sleep mode. The 34932 has output current limiting (via constant OFF- time PWM current regulation), output short-circuit detection with latch-OFF, and overtemperature detection with latch- OFF. Once the device is latched-OFF due to a fault condition, either of the disable inputs (D1 or EN/D2), or VPWR must be to clear the status flag. Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering. The current limiting scheme is unique in that it incorporates a junction temperature- dependent current limit threshold. This means the current limit threshold is reduced to around 4.2 A as the junction temperature increases above 160 °C. When the temperature is above 175 °C, overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to continue operating for short periods of time (<30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. FUNCTIONAL PIN DESCRIPTION POWER GROUND AND ANALOG GROUND (PGND AND AGND) The power and analog ground pins should be connected together with a very low-impedance connection. POSITIVE POWER SUPPLY (VPWR) VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces, offering as low an impedance as possible between pins. STATUS FLAG (SF) This pin is the device fault status output. This output is an active LOW open drain structure requiring a pull-up resistor to VDD. The maximum VDD is <7.0 V. Refer to Table 5, Truth Table, for the SF Output status definition. INPUT 1,2 AND DISABLE INPUT 1 (IN1, IN2, AND D1) These pins are input control pins used to control the outputs. These pins are 3.0 V/5.0 V CMOS-compatible inputs with hysteresis. IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 input is used to tri-state disable the H-Bridge outputs. When D1 is SET (D1 = logic HIGH) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 3, Static Electrical Characteristics. H-BRIDGE OUTPUT (OUT1, OUT2) These pins are the outputs of the H-bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1, and EN/D2 inputs. The outputs have PWM current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time tB) is incorporated to distinguish between load currents higher than the ILIM threshold and short circuit currents. This timer is activated at each output transition. CHARGE PUMP CAPACITOR (CCP) This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is from 30 to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly without the external reservoir capacitor. |
Số phần tương tự - MC34932 |
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Mô tả tương tự - MC34932 |
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