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AD5280BRU20-REEL7 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD5280BRU20-REEL7 bảng dữ liệu(HTML) 4 Page - Analog Devices |
4 / 28 page AD5280/AD5282 Rev. C | Page 4 of 28 Parameter Symbol Conditions Min Typ1 Max Unit Total Harmonic Distortion THDW VA = 1 V rms, RAB = 20 kΩ 0.014 % VB = 0 V dc, f = 1 kHz VW Settling Time tS VA = 5 V, VB = 5 V, ±1 LSB error band 5 μs Crosstalk CT VA = VDD, VB = 0 V, measure VW1 with adjacent RDAC making full-scale code change 15 nV-s Analog Crosstalk CTA Measure VW1 with VW2 = 5 V p-p @ f = 10 kHz −62 dB Resistor Noise Voltage eN_WB RWB = 20 kΩ, f = 1 kHz 18 nV/√Hz INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11 SCL Clock Frequency fSCL 0 400 kHz tBUF Bus Free Time Between Stop and Start t1 1.3 μs tHD:STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is generated 0.6 μs tLOW Low Period of SCL Clock t3 1.3 μs tHIGH High Period of SCL Clock t4 0.6 μs tSU:STA Setup Time for Start Condition t5 0.6 μs tHD:DAT Data Hold Time t6 0 0.9 μs tSU:DAT Data Setup Time t7 100 ns tF Fall Time of Both SDA and SCL Signals t8 300 ns tR Rise Time of Both SDA and SCL Signals t9 300 ns tSU:STO Setup Time for STOP Condition t10 0.6 μs 1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use VDD = 5 V. 10 See timing diagram (Figure 3) for location of measured values. 11 Standard I2C mode operation is guaranteed by design. t1 t2 t3 t8 t8 t9 t9 t6 t4 t7 t5 t2 t10 PS S SCL SDA P Figure 3. Detailed Timing Diagram |
Số phần tương tự - AD5280BRU20-REEL7 |
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Mô tả tương tự - AD5280BRU20-REEL7 |
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