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AD7823 bảng dữ liệu(PDF) 7 Page - Analog Devices |
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AD7823 bảng dữ liệu(HTML) 7 Page - Analog Devices |
7 / 11 page AD7823 –7– REV. C When using the pseudo differential input scheme the signal on VIN– must not vary by more than a 1/2 LSB during the conver- sion process. If the signal on VIN– varies during conversion, the conversion result will be incorrect. For single ended operation, VIN– is always connected to AGND. Figure 9 shows the AD7823 pseudo differential input being used to make a unipolar dc current mea- surement. A sense resistor is used to convert the current to a voltage, and the voltage is applied to the differential input as shown. VDD RSENSE RL VIN+ VIN– AD7823 Figure 9. DC Current Measurement Scheme DC Acquisition Time The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the end of a conversion there is a settling time associated with the sampling circuit. This settling time lasts approximately 100 ns. The analog signal on VIN+ is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns. Figure 10 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R2 represents the source impedance of a buffer amplifier or resistive network; R1 is an internal multiplexer resistance and C1 is the sampling capacitor. C1 3.5 F R1 125 VIN+ R2 Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (tCHARGE) is given by the follow- ing formula: tCHARGE = 6.2 × (R2 + 125 Ω) × 3.5 pF For small values of source impedance, the settling time associated with the sampling circuit (100 ns) is, in effect, the acquisition time of the ADC. For example, with a source impedance (R2) of 10 Ω, the charge time for the sampling capacitor is approxi- mately 2 ns. The charge time becomes significant for source impedances of 4.6 k Ω and greater. AC Acquisition Time In ac applications it is recommended to always buffer analog input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor- mance can generally be achieved by using an external 1 nF capacitor on VIN+. ADC TRANSFER FUNCTION The output coding of the AD7823 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256. The ideal trans- fer characteristic for the AD7823 is shown in Figure 11 below. 000...010 000...001 000...000 0V +VREF –1LSB ANALOG INPUT 111...111 111...110 111...000 011...111 1LSB 1LSB = VREF/256 Figure 11. Transfer Characteristic |
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