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AD5666 bảng dữ liệu(PDF) 5 Page - Analog Devices

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Giải thích chi tiết về linh kiện  Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
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Data Sheet
AD5024/AD5044/AD5064
Rev. F | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and
Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
Symbol
Min
Typ
Max
Unit
SCLK Cycle Time
t1
20
ns
SCLK High Time
t2
10
ns
SCLK Low Time
t3
10
ns
SYNC to SCLK Falling Edge Setup Time
t4
17
ns
Data Setup Time
t5
5
ns
Data Hold Time
t6
5
ns
SCLK Falling Edge to SYNC Rising Edge
t7
5
30
ns
Minimum SYNC High Time (Single Channel Update)
t8
3
µs
Minimum SYNC High Time (All Channel Update)
t8
8
µs
SYNC Rising Edge to SCLK Fall Ignore
t9
17
ns
LDAC Pulse Width Low
t10
20
ns
SCLK Falling Edge to LDAC Rising Edge
t11
20
ns
CLR Minimum Pulse Width Low
t12
10
ns
SCLK Falling Edge to LDAC Falling Edge
t13
10
ns
CLR Pulse Activation Time
t14
10.6
µs
SCLK Rising Edge to SDO Valid
t152, 3
22
ns
SCLK Falling Edge to SYNC Rising Edge
t162
5
ns
SYNC Rising Edge to SCLK Rising Edge
t172
8
ns
SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update)
t182
2
µs
SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update)
t182
8
µs
Power-up Time4
4.5
µs
1
Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Daisy-chain mode only.
3
Measured with the load circuit of Figure 3. t15 determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.
4
Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
Circuit and Timing Diagrams
2mA
IOL
2mA
IOH
TO OUTPUT
PIN
CL
50pF
2
VOH (MIN) + VOL (MAX)
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications


Số phần tương tự - AD5666

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Mô tả tương tự - AD5666

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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Analog Devices
AD5064 AD-AD5064_15 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
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AD5024 AD-AD5024_15 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5044 AD-AD5044_15 Datasheet
2Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
Rev. F
AD5024 AD-AD5024 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP
REV. 0
AD5025 AD-AD5025_15 Datasheet
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AD5025 AD-AD5025_08 Datasheet
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   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
REV. 0
AD5065 AD-AD5065_15 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
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AD5045 AD-AD5045_15 Datasheet
1Mb / 28P
   Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP
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AD5066 AD-AD5066_15 Datasheet
617Kb / 24P
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AD5066BRUZ AD-AD5066BRUZ Datasheet
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