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AD1835AAS bảng dữ liệu(PDF) 11 Page - Analog Devices |
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AD1835AAS bảng dữ liệu(HTML) 11 Page - Analog Devices |
11 / 24 page REV. A AD1835A –11– (continued from page 1) Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit - modulators and decimation filters. The AD1835A also contains an on-chip reference with a nominal value of 2.25 V. The AD1835A contains a flexible serial interface that allows glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1835A can be configured in left-justified, right-justified, I 2S, or DSP com- patible serial modes. Control of the AD1835A is achieved by an SPI ® compatible serial port. While the AD1835A can be oper- ated from a single 5 V supply, it also features a separate supply pin for its digital interface which allows the device to be inter- faced to other devices using 3.3 V power supplies. The AD1835A is available in a 52-lead MQFP package and is specified for the industrial temperature range of –40 °C to +85°C. FUNCTIONAL OVERVIEW ADCs There are two ADC channels in the AD1835A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate of up to 96 kHz. The ADCs include on-board digital decimation filters with 120 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 kHz opera- tion) or 64 (for 96 kHz operation). ADC peak level information for each ADC may be read from the ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a 6-bit word with a maximum range of 0 dB to –63 dB and a resolution of 1 dB. The registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. Refer to the register description for details of the format. The two ADC channels have a com- mon serial bit clock and a left-right framing clock. The clock signals are all synchronous with the sample rate. The ADC digital pins, ABCLK and ALRCLK, can be set to operate as inputs or outputs by connecting the M/S pin to ODVDD or DGND, respectively. When the pins are set as outputs, the AD1835A will generate the timing signals. When the pins are set as inputs, the timing must be generated by the external audio controller. DACs The AD1835A has eight DAC channels arranged as four inde- pendent stereo pairs, with eight fully differential analog outputs for improved noise and distortion performance. Each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one of the packed data modes can be used to access all eight channels on a single TDM data pin. A stereo replicate feature is included where the DAC data sent to the first DAC pair is also sent to the other DACs in the part. The AD1835A can accept DAC data at a sample rate of 192 kHz on DAC 1 only. The stereo replicate fea- ture can then be used to copy the audio data to the other DACs. Each set of differential output pins sits at a dc level of VREF and swings 1.4 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD pin should be connected to an external grounded capacitor. This pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. In some cases, this capacitor may be eliminated with little effect on performance. DAC and ADC Coding The DAC and ADC output data stream is in a twos complement encoded format. The word width can be selected from 16 bit, 20 bit, or 24 bit. The coding scheme is detailed in Table I. Table I. Coding Scheme Code Level 01111......1111 +FS 00000......0000 0 (Ref Level) 10000......0000 –FS AD1835A CLOCKING SCHEME By default, the AD1835A requires an MCLK signal that is 256 times the required sample frequency up to a maximum of 12.288 MHz. The AD1835A uses a clock scaler to double the clock frequency for use internally. The default setting of the clock scaler is Multiply by 2. The clock scaler can also be set Multiply by 1 (bypass) or by 2/3. The clock scaler is controlled by programming the bits in the ADC Control 3 register. The internal MCLK signal, IMCLK, should not exceed 24.576 MHz in order to ensure correct operation. The MCLK of the AD1835A should remain constant during normal operation of the DAC and ADC. If it is necessary to change the MCLK rate, then the AD1835A should be reset. Additionally, if the MCLK scaler needs to be modified so that the IMCLK doesn’t exceed 24.576 MHz, this should be done during the internal reset phase of the AD1835A by programming the bits in the first 3072 MCLK periods following the reset. Selecting DAC Sampling Rate The AD1835A DAC engine has a programmable interpolator that allows the user to select different interpolation rates based on the required sample rate and MCLK value available. Table II shows the settings required for sample rates based on a fixed MCLK of 12.288 MHz. Table II. DAC Sample Rate Settings Sample Rate Interpolator Rate DAC Control 1 Register 48 kHz 8x 000000xxxxxxxx00 96 kHz 4x 000000xxxxxxxx01 192 kHz 2x 000000xxxxxxxx10 Selecting an ADC Sample Rate The AD1835A ADC engine has a programmable decimator, which allows the user to select the sample rate based on the MCLK value. By default, the output sample rate is IMCLK/ 512. To achieve a sample rate of IMCLK/256, the sample rate bit in the ADC Control 1 register should be set as shown in Table III. |
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