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ADM1073 bảng dữ liệu(PDF) 7 Page - Analog Devices |
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ADM1073 bảng dữ liệu(HTML) 7 Page - Analog Devices |
7 / 24 page Data Sheet ADM1073 Rev. B | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADM1073 TOP VIEW (Not to Scale) RESTART 1 VIN 2 PWRGD 3 SS 4 SENSE 5 SHDN TIMER UV OV DRAIN 14 13 12 11 10 VEE 6 LATCHED 7 GATE SPLYGD 9 8 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin Number Mnemonic Function 1 RESTART Input Pin. Edge-triggered 5-second shutdown and automatic restart. 2 VIN Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF capacitor to VEE is recommended on the VIN pin. 3 PWRGD Open Drain Output. Signals that the hot swap is complete. 4 SS Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current profile. This pin can be overdriven to alter the current limit control loop threshold. 5 SENSE Voltage Input from External Sense Resistor. 6 VEE Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection. 7 LATCHED Open Drain Output. Signals the end of the PWM retry period after a current fault. 8 SPLYGD Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage window. 9 GATE Output to External FET Gate Drive. 10 DRAIN Analog Input for Monitoring of FET Drain Voltage. 11 OV Input Pin for Overvoltage Detection Circuitry. 12 UV Input Pin for Undervoltage Detection Circuitry. 13 TIMER Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the PWM on-time, and the PWM duty cycle. 14 SHDN Input Pin. Level-triggered device shutdown and reset. |
Số phần tương tự - ADM1073 |
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Mô tả tương tự - ADM1073 |
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