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ADE7752AARZ-RL bảng dữ liệu(PDF) 4 Page - Analog Devices

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ADE7752/ADE7752A
Rev. C | Page 4 of 24
TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to T
= –40°C to +85°C, unless otherwise noted
.
1, 2
MAX
Table 2.
Parameter
Conditions
Spec
Unit
t
F1 and F2 Pulse Width (Logic High).
275
ms
1
3
t
Output Pulse Period. See the Transfer Function section.
See Table 6.
sec
2
t
Time between F1 Falling Edge and F2 Falling Edge.
1/2 t
3
2
sec
t
CF Pulse Width (Logic High).
96
ms
4
3, 4
t
CF Pulse Period. See the Transfer Function and the Frequency Outputs sections.
See Table 7.
sec
5
5
t
Minimum Time Between the F1 and F2 Pulse.
CLKIN/4
sec
6
1 Sample tested during initial release and after any redesign or process change that may affect this parameter.
2 See Figure 2.
3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
4 CF is not synchronous to F1 or F2 frequency outputs.
5 The CF pulse is always 1 μs in the high frequency mode.
F1
F2
CF
t1
t6
t2
t3
t4
t5
Figure 2. Timing Diagram for Frequency Outputs


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