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MCP6N11-010 bảng dữ liệu(PDF) 10 Page - Microchip Technology

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MCP6N11
DS25073A-page 10
© 2011 Microchip Technology Inc.
1.5
Explanation of DC Error Specs
1.5.1
INPUT OFFSET RELATED ERRORS
The input offset error (VE) is extracted from input offset
measurements (see Section 1.4.1 “Input Offset Test
Circuit”), based on Equation 1-1:
EQUATION 1-4:
VE has several terms, which assume a linear response
to changes in VDD, VSS, VCM, VOUT and TA (all of which
are in their specified ranges):
EQUATION 1-5:
Equation 1-2 shows how VE affects VOUT.
1.5.2
INPUT OFFSET COMMON MODE
NON-LINEARITY
The input offset error (VE) changes non-linearly with
VCM. Figure 1-8 shows VE vs. VCM, as well as a linear
fit line (VE_LIN) based on VOS and CMRR. The op amp
is in standard conditions (
ΔVOUT =0, VDM =0, etc.).
VCM is swept from VIVL to VIVH. The test circuit is in
Section 1.4.1 “Input Offset Test Circuit” and VE is
calculated using Equation 1-4.
FIGURE 1-8:
Input Offset Error vs.
Common Mode Input Voltage.
Based on the measured VE data, we obtain the
following linear fit:
EQUATION 1-6:
The remaining error (
ΔVE) is described by the Common
Mode Non-Linearity spec:
EQUATION 1-7:
The same common mode behavior applies to VE when
VREF is swept, instead of VCM, since both input stages
are designed the same:
EQUATION 1-8:
1.5.3
DIFFERENTIAL GAIN ERROR AND
NON-LINEARITY
The differential errors are extracted from differential
gain measurements (see Section 1.4.2 “Differential
Gain Test Circuit”), based on Equation 1-2. These
errors are the differential gain error (gE) and the input
offset error (VE, which changes non-linearly with VDM):
EQUATION 1-9:
These errors are adjusted for the expected output, then
referred back to the input, giving the differential input
error (VED) as a function of VDM:
EQUATION 1-10:
V
E
V
M
V
REF
G
DM 1gE
+
()
---------------------------------
=
Where:
PSRR
, CMRR and A
OL are in units of V/V
ΔT
A is in units of °C
VDM =0
V
E
V
OS
ΔV
DD
ΔV
SS
PSRR
---------------------------------
ΔV
CM
CMRR
-----------------
ΔV
REF
CMRR
-----------------
++
+
=
ΔV
OUT
A
OL
-----------------
ΔT
A
ΔV
OS
ΔT
A
-------------
++
V1
V3
VE, VE_LIN (V)
VCM (V)
VIVL
VIVH
VDD/2
V2
VE_LIN
VE
ΔVE
Where:
V
E_LIN
V
OS
V
CM
V
DD 2
CMRR
-----------------------------------
+
=
V
OS
V
2
=
1
CMRR
-----------------
V
3
V
1
V
IV H
V
IVL
------------------------------
=
Where:
INL
CM
max
ΔV
E
V
IVH
V
IV L
------------------------------
=
ΔV
E
V
E
V
E_LIN
=
V
E_LIN
V
OS
V
REF
V
DD 2
CMRR
-------------------------------------
+
=
INL
CM
max
ΔV
E
V
IVH
V
IVL
------------------------------
=
G
DM
1R
F RG
+
=
V
M
G
DM 1gE
+
() V
DM
V
+
E
()
=
V
ED
V
M
G
DM
------------V
DM
=


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