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ADS42JB69IRGCT bảng dữ liệu(PDF) 7 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  Dual-Channel, 14- and 16-Bit, 250-MSPS Analog-to-Digital Converters
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ADS42JB49
ADS42JB69
www.ti.com
SLAS900E – OCTOBER 2012 – REVISED AUGUST 2013
TIMING CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, IOVDD = 1.8 V, 50% clock duty cycle, –1-
dBFS differential analog input, and sampling rate = 250 MSPS, unless otherwise noted. Minimum and maximum values are
across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, and
IOVDD = 1.8 V. See Figure 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SAMPLE TIMING CHARACTERISTICS
Aperture delay
0.4
0.7
1.1
ns
Between two channels on the same device
±70
ps
Aperture delay matching
Between two devices at the same temperature and supply
±150
ps
voltage
Aperture jitter
85
fS rms
Time to valid data after coming out of STANDBY mode
50
200
µs
Wake-up time
Time to valid data after coming out of global power-down
250
1000
µs
tSU_SYNC~
Setup time for SYNC~
Referenced to input clock rising edge
400
ps
tH_SYNC~
Hold time for SYNC~
Referenced to input clock rising edge
100
ps
tSU_SYSREF
Setup time for SYSREF
Referenced to input clock rising edge
400
ps
tH_SYSREF
Hold time for SYSREF
Referenced to input clock rising edge
100
ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval
320
1667
ps
Serial output data rate
3.125
Gbps
2.5 Gbps (10x mode, fS = 250 MSPS)
0.28
P-PUI
Total jitter
3.125 Gbps (20x mode, fS = 156.25 MSPS)
0.3
P-PUI
Rise and fall times measured from 20% to 80%,
Data rise time,
tR, tF
differential output waveform,
105
ps
data fall time
600 Mbps
≤ bit rate ≤ 3.125 Gbps
Table 2. Latency in Different Modes(1)(2)
MODE
PARAMETER
LATENCY (N Cycles)
TYPICAL DATA DELAY (tD, ns)
ADC latency
23
0.65 × tS + 3
Normal OVR latency
14
6.7
10x
Fast OVR latency
9
6.7
from SYNC~ falling edge to CGS phase(3)
16
0.65 × tS + 3
from SYNC~ rising edge to ILA sequence(4)
25
0.65 × tS + 3
ADC latency
22
0.85 × tS + 3
Normal OVR latency
14
6.7
20x
Fast OVR latency
9
6.7
from SYNC~ falling edge to CGS phase(3)
15
0.85 × tS + 3
from SYNC~ rising edge to ILA sequence(4)
16
0.85 × tS + 3
(1)
Overall latency = latency + tD.
(2)
tS is the time period of the ADC conversion clock.
(3)
Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15
clock cycles in 20x mode.
(4)
Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and
11 clock cycles in 20x mode.
Copyright © 2012–2013, Texas Instruments Incorporated
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