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LM73CIMKX-0 bảng dữ liệu(PDF) 6 Page - Texas Instruments

tên linh kiện LM73CIMKX-0
Giải thích chi tiết về linh kiện  LM73 2.7V, SOT, 11-to-14 Bit Digital Temperature Sensor with 2-Wire Interface
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Trang chủ  http://www.ti.com
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LM73CIMKX-0 bảng dữ liệu(HTML) 6 Page - Texas Instruments

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VIH
VIL
SMBCLK
P
S
VIH
VI
L
SMBDAT
tBUF
tHD;STA
tLOW
tR
tHD;DAT
tHIGH
tF
tSU;DAT
tSU;STA
tSU;STO
P
S
LM73
SNIS141D – OCTOBER 2005 – REVISED MAY 2009
www.ti.com
LOGIC ELECTRICAL CHARACTERISTICS - SMBus DIGITAL SWITCHING CHARACTERISTICS
Unless otherwise noted, these specifications apply for VDD = +2.7 V to +5.5 V, CL (load capacitance) on output lines = 400 pF.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical(1)
Limits(2)
Units
(Limit)
fSMB
SMBus Clock Frequency
No minimum clock frequency
400
kHz (max)
if Time-Out feature is
disabled.
tLOW
SMBus Clock Low Time
300
ns (min)
tHIGH
SMBus Clock High Time
300
ns (min)
tF;SMBO
Output Fall Time(3)
CL = 400 pF
250
ns (max)
IPULL-UP ≤ 3 mA
tTIMEOUT
SMBDAT and SMBCLK Time Low for Reset of
15
ms (min)
Serial Interface(4)
45
ms (max)
tSU;DAT
Data In Setup Time to SMBCLK High
100
ns (min)
tHD;DATI
Data Hold Time: Data In Stable after SMBCLK
0
ns (min)
Low
tHD;DATO
Data Hold Time: Data Out Stable after SMBCLK
30
ns (min)
Low
tHD;STA
Start Condition SMBDAT Low to SMBCLK Low
60
ns (min)
(Start condition hold before the first clock falling
edge)
tSU;STO
Stop Condition SMBCLK High to SMBDAT Low
50
ns (min)
(Stop Condition Setup)
tSU;STA
SMBus Repeated Start-Condition Setup Time,
50
ns (min)
SMBCLK High to SMBDAT Low
tBUF
SMBus Free Time Between Stop and Start
1.2
µs (min)
Conditions
tPOR
Power-On Reset Time(5)
1
ms (max)
(1)
Typicals are at TA = 25°C and represent most likely parametric norm.
(2)
Limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3)
The output fall time is measured from (VIH;MIN + 0.15V) to (VIL;MAX - 0.15V).
(4)
Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM73's SMBus state machine,
setting SMBDAT and SMBCLK pins to a high impedance state.
(5)
Represents the time from VDD reaching the power-on-reset level to the LM73 communications being functional. After an additional time
equal to one temperature conversion time, valid temperature will be available in the TEMPERATURE DATA REGISTER.
Figure 2. SMBus Communication
6
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Links: LM73


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