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4 / 86 page MCP4706/4716/4726 DS22272C-page 4 © 2011-2012 Microchip Technology Inc. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5 kΩ from VOUT to GND, CL = 100 pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions Power Requirements Input Voltage VDD 2.7 — 5.5 V Input Current IDD — 210 400 µA VREF1:VREF0 = 00, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 — 210 400 µA VREF1:VREF0 = 11, VREF = VDD, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0x000 Power-Down Current IDDP — 0.09 2 µA PD1:PD0 = 01 (Note 6), VOUT not connected Power-On Reset Threshold VPOR — 2.2 — V RAM retention voltage, (VRAM) < VPOR Power-Up Ramp Rate VRAMP 1— — V/S (Note 1, Note 4) DC Accuracy Offset Error VOS ±0.02 0.75 % of FSR Code = 0x000h VREF1:VREF0 = 00, G = 0 Offset Error Temperature Coefficient VOS/°C — ±1 — ppm/°C -40°C to +25°C — ±2 — ppm/°C +25°C to +85°C Zero-Scale Error EZS —0.13 2.0 LSb MCP4706, Code = 0x00h — 0.52 7.7 LSb MCP4716, Code = 0x000h — 2.05 30.8 LSb MCP4726, Code = 0x000h Full-Scale Error EFS —0.3 5.2 LSb MCP4706, Code = 0xFFh — 1.1 20.5 LSb MCP4716, Code = 0x3FFh — 4.1 82.0 LSb MCP4726, Code = 0xFFFh Gain Error (Note 2) gE -2 -0.10 2 % of FSR MCP4706, Code = 0xFFh VREF1:VREF0 = 00, G = 0 -2 -0.10 2 % of FSR MCP4716, Code = 0x3FFh VREF1:VREF0 = 00, G = 0 -2 -0.10 2 % of FSR MCP4726, Code = 0xFFFh VREF1:VREF0 = 00, G = 0 Gain Error Drift ΔG/°C — -3 — ppm/°C Resolution n 8 bits MCP4706 10 bits MCP4716 12 bits MCP4726 INL Error (Note 7) INL -0.907 ±0.125 +0.907 LSb MCP4706 (codes: 6 to 250) -3.625 ±0.5 +3.625 LSb MCP4716 (codes: 25 to 1000) -14.5 ±2 +14.5 LSb MCP4726 (codes: 100 to 4000) DNL Error (Note 7) DNL -0.05 ±0.0125 +0.05 LSb MCP4706 (codes: 6 to 250) -0.188 ±0.05 +0.188 LSb MCP4716 (codes: 25 to 1000) -0.75 ±0.2 +0.75 LSb MCP4726 (codes: 100 to 4000) Note 1: This parameter is ensured by design and is not 100% tested. 2: This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of VDD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = 10, and ‘11’ configurations should have the same current. 7: VDD = VREF = 5.5V. |
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