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ADS4245 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS4245 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 67 page ADS4229 SBAS550B – JUNE 2011 – REVISED AUGUST 2012 www.ti.com TIMING REQUIREMENTS: LVDS and CMOS Modes Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V. Table 2. LVDS and CMOS Modes(1) PARAMETER DESCRIPTION MIN TYP MAX UNIT tA Aperture delay 0.5 0.8 1.1 ns Aperture delay matching Between the two channels of the same device ±70 ps Between two devices at the same temperature and Variation of aperture delay ±150 ps DRVDD supply tJ Aperture jitter 140 fS rms Time to valid data after coming out of STANDBY 50 100 µs mode Wakeup time Time to valid data after coming out of GLOBAL 100 500 µs power-down mode Clock Default latency after reset 16 cycles ADC latency(2) Clock Digital functions enabled (EN DIGITAL = 1) 24 cycles DDR LVDS MODE(3) tSU Data setup time Data valid(4) to zero-crossing of CLKOUTP 0.6 0.88 ns Zero-crossing of CLKOUTP to data becoming tH Data hold time 0.33 0.55 ns invalid(4) Input clock rising edge cross-over to output clock tPDI Clock propagation delay 5.0 6.0 7.5 ns rising edge cross-over Duty cycle of differential clock, (CLKOUTP- LVDS bit clock duty cycle 48 % CLKOUTM) Rise time measured from –100 mV to +100 mV tRISE, Data rise time, Fall time measured from +100 mV to –100 mV 0.13 ns tFALL Data fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS Rise time measured from –100 mV to +100 mV tCLKRISE, Output clock rise time, Fall time measured from +100 mV to –100 mV 0.13 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 250 MSPS PARALLEL CMOS MODE Input clock rising edge cross-over to output clock tPDI Clock propagation delay 4.5 6.2 8.5 ns rising edge cross-over Duty cycle of output clock, CLKOUT Output clock duty cycle 50 % 1 MSPS ≤ Sampling frequency ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD tRISE, Data rise time, Fall time measured from 80% to 20% of DRVDD 0.7 ns tFALL Data fall time 1 MSPS ≤ Sampling frequency ≤ 200 MSPS Rise time measured from 20% to 80% of DRVDD tCLKRISE, Output clock rise time Fall time measured from 80% to 20% of DRVDD 0.7 ns tCLKFALL Output clock fall time 1 MSPS ≤ Sampling frequency ≤ 200 MSPS (1) Timing parameters are ensured by design and characterization and not tested in production. (2) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (3) Measurements are done with a transmission line of 100- Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (4) Data valid refers to a logic high of +100 mV and a logic low of –100 mV. 8 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Links: ADS4229 |
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