Vias couple thermal energy to copper plane on bottom layer to transfer heat away from package.

LM98555

SNAS290D – DECEMBER 2005 – REVISED APRIL 2013

www.ti.com

Figure 7. 2 Layer PCB

In multi-layer board applications, one or more internal planes are usually dedicated as a ground plane.

Connecting the thermal pad to this ground plane with vias will usually provide adequate heat management. In 2

layer boards, it is important to provide a large heat spreading pad on the opposite side of the board. The vias will

provide a good thermal connection between the pad under the IC, and the heat spreading pad on the bottom of

the board. Thermal modelling can be done using the

θ junction to pad information provided, to calculate the

required area of copper based on the ambient temperature of the system, and the calculated amount of thermal

dissipation in the LM98555.

POWER DISSIPATION

The amount of power dissipated in the device can be determined by considering the following factors:

•

Power dissipated delivering energy to the load capacitance

•

Power dissipated delivering energy to parasitic capacitance

•

Power dissipated due to leakage in the IC

The amount of power dissipated due to leakage is very small in this CMOS device. Most of the power will be due

to the load capacitance being switched, with a small additional amount caused by the parasitic capacitance of the

output circuitry, output pins, and PCB traces. A typical parasitic capacitance would be on the order of 5 pF. Since

the load capacitance will be on the order of 100 pF or more, this usually dominates the power dissipation

calculation. The following equation can be used to calculate the power dissipation due to capacitive switching of

the loads:

P = Sum[Output Frequency x Load Capacitance x Output Voltage Squared] (summed for all outputs)

INPUT SIGNALS

Care should be taken to match the trace lengths between timing signals that require low skew. Usually, the P1A

and P2A signals will be the most critical. In some applications, the timing of P2B with respect to P1A and P2A

can also be important, and that input trace should also be carefully designed.

Trace shape and width should also be carefully controlled. The trace geometry will determine the characteristic

impedance of each trace. The impedance should be set to give reasonable immunity to noise coupling into the

trace. With a known trace impedance, the signals can be terminated using a series resistor at the source that is

equal to the characteristic impedance. This will provide a signal with minimum overshoot and ringing, and will

contribute to better performance of the final signal reaching the CCD.

OUTPUT CONNECTIONS AND LOADING EXAMPLES

The LM98555 can be used with a wide variety of different CCD sensors. The P1Aoutx and P2Aoutx outputs can

be selectively enabled to provide 2, 4, 6, or 8 drivers. This allows the available drive strength to be optimized for

the sensor and application. Connecting multiple outputs together in parallel as shown in the typical application

circuit provides lower drive impedance as needed to suit the load being driven. When driving smaller loads, lower

switching noise will be generated if the minimum necessary outputs are enabled and used.

The output signal traces should also be designed for a known impedance. Source terminating resistors should be

used in series with each output to provide good matching to the trace characteristic impedance. The resistors

should be located as close as possible to each output pin. If multiple outputs will be combined to drive a single

load pin, the output signals should be combined after the termination resistors. This will provide the best

summing of adjacent outputs. The combined signal should then pass through an EMI type ferrite bead. This

component can be selected to change the bandwidth or shape of the clocking signal to achieve the best CCD

transfer efficiency.

8

Submit Documentation Feedback

Copyright © 2005–2013, Texas Instruments Incorporated

Product Folder Links: LM98555