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AD5504BRUZ-REEL bảng dữ liệu(PDF) 6 Page - Analog Devices

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AD5504BRUZ-REEL bảng dữ liệu(HTML) 6 Page - Analog Devices

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AD5504
Data Sheet
Rev. B | Page 6 of 20
TIMING CHARACTERISTICS
VDD = 30 V, VLOGIC = 2.3 V to 5.5 V and −40°C < TA < +105°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Limit1
Unit
Test Conditions/Comments
t12
60
ns min
SCLK cycle time
t2
10
ns min
SCLK high time
t3
10
ns min
SCLK low time
t4
25
ns min
SYNC falling edge to SCLK rising edge setup time
t5
15
ns min
Data setup time
t6
5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
20
ns min
Minimum SYNC high time
t9
20
ns min
LDAC pulse width low
t10
50
ns min
SCLK falling edge to LDAC rising edge
t11
15
ns min
CLR pulse width low
t12
100
ns typ
CLR pulse activation time
t13
20
μs typ
ALARM clear time
t14
110
ns min
SCLK cycle time in read mode
t153
55
ns max
SCLK rising edge to SDO valid
t163
25
ns min
SCLK to SDO data hold time
t174
50
μs max
Power-on reset time (this is not shown in the timing diagrams)
t185
50
μs max
Power-on time (this is not shown in the timing diagrams)
t19
5
μs typ
ALARM clear to output amplifier turn on (this is not shown in the timing
diagrams)
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 16.667 MHz.
3
Under load conditions shown in Figure 2.
4
Time from when the VDD/VLOGIC supplies are powered-up to when a digital interface command can be executed.
5
Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.
VOH (MIN) – VOL (MAX)
2
200µA
IOL
200µA
IOH
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for SDO Timing Diagram


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