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AD1954YS bảng dữ liệu(PDF) 9 Page - Analog Devices

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AD1954
–9–
An extensive SPI port allows click-free parameter updates, along
with read-back capability from any point in the algorithm flow.
The AD1954 includes ADI’s patented multibit - DAC architec-
ture.This architecture provides 112 dB SNR and dynamic range
and THD+N of –100 dB.These specifications allow the AD1954
to be used in applications ranging from low-end boom boxes to
high-end professional mixing/editing systems.
The AD1954 also has a digital output that allows it to be used
purely as a DSP.This digital output can also be used to drive an
external DAC to extend the number of channels beyond the three
that are provided on the chip.
This chip can be used with either its default signal processing
program or with a custom user-designed program. Graphical pro-
gramming tools are available from ADI for custom programming.
FEATURES
The AD1954 is comprised of a 26-bit DSP (48 bits with double
precision) for interpolation and audio processing, three multibit
- modulators, and analog output drive circuitry. Other features
include an on-chip parameter RAM that uses a safe-upload feature
for transparent and simultaneous updates of filter coefficients and
digital de-emphasis filters. Also, on-chip input selectors allow up
to three sources of serial data and master clock to be selected.
The 3-channel configuration is especially useful for 2.1 playback
systems that include two satellite speakers and a subwoofer.
The default program allows for independent equalization and
compression/limiting for the satellite and subwoofer outputs.
Figure 1 shows the block diagram of the device.
The AD1954 contains a program RAM that boots from an internal
program ROM on power-up. Signal processing parameters are
stored in a 256-location parameter RAM, which is initialized on
power-up by an internal boot ROM. New values are written to
the parameter RAM using the SPI port.The values stored in the
parameter RAM control the IIR equalization filters, the dual-
band compressor/limiter, the delay values, and the settings of the
stereo spreading algorithm.
The AD1954 has a very sophisticated SPI port that supports
complete read/write capability of both the program and the para-
meter RAM.Two control registers are also provided to control
the chip serial modes and various other optional features. Hand-
shaking is also included for ease of memory uploads/downloads.
The AD1954 contains four independent data capture circuits,
which can be programmed to tap the signal flow of the processor
at any point in the DSP algorithm flow.These captured signals
can be accessed either through a separate serial out pin (i.e., that
can be connected to an external DAC or DSP) or by reading from
the data capture SPI registers.This allows the basic functionality
of the AD1954 to be easily extended.
The processor core in the AD1954 has been designed from the
ground up for straightforward coding of sophisticated compres-
sion/limiting algorithms.The AD1954 contains two independent
compressor/limiters with rms based amplitude detection and
attack/hold/release controls, together with an arbitrary compression
curve that is loaded by the user into a look-up table that resides
in the parameter RAM.The compressor also features look-ahead
compression that prevents compressor overshoots.
GENERAL DESCRIPTION (continued from page 1)
3:1
AUDIO
DATA
MUX1
3
3
SPI PORT
3:1
MCLK
MUX1
DAC – L
COEFFICIENT
ROM
64  22
26  22
DSP CORE
DATA FORMAT:
3.23 (SINGLE PRECISION)
3.45 (DOUBLE PRECISION)
3
3
ANALOG
OUTPUTS
MASTER
CLOCK I/O
GROUP
DCSOUT
SPI I/O
GROUP
3
SERIAL
IN1
DATA MEMORY, 512  26
CONTROL
REGISTERS
TRAP REG.
(I2S, SPI)
SAFELOAD
REGISTERS
PROGRAM
RAM
512  35
PARAMETER
RAM
256  22
MEMORY CONTROLLERS
DAC – R
DAC – SW2
BIAS
ANALOG
BIAS GROUP
RESETB
MUTE DE-EMPHASIS
ZEROFLAG
NOTES
1CONTROLLEDTHROUGH SPI CONTROL REGISTERS.
2DAC DOES NOT USE DIGITAL INTERPOLATION.
SERIAL DATA I/O
GROUP
DCSOUT TRAP
AUX SERIAL
DATA INPUT
MCLK
GENERATOR1
(256
fS/512 fS IN)
256
fS/512 fS OUT
VOLTAGE
REFERENCE
VREF
DVDD
AVDD
ODVDD
3
FILTCAP
AGND
DGND
3
2
Figure 1. Block Diagram
REV. A


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