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FSTUD32450G bảng dữ liệu(PDF) 1 Page - Fairchild Semiconductor |
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1 / 13 page © 2005 Fairchild Semiconductor Corporation DS500447 www.fairchildsemi.com August 2001 Revised October 2006 FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting General Description The Fairchild Universal Bus Switch FSTUD32450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed CMOS TTL-compatible bus switching. The low On Resis- tance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The FSTUD32450 is designed to allow “customer” configu- ration control of the enable connections. The device can be organized as either a ten 4-bit, eight 5-bit, four 10-bit, two 20-bit or one 40-bit enabled bus switch. Also achievable are 8-bit and 16-bit enabled configurations (see Functional Description). The device's bit configuration is controlled through select pin logic. (see Truth Table). When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild's integrated Undershoot Hardened Circuit ( UHC® ¥) senses undershoot at the I/O, and responds by preventing voltage differentials from developing and turning the switch on. Another innovative device feature is the addition of a level shifting select pin, “S2 and S5”. When S2 and S5 are LOW, the device behaves as a standard N-MOS switch. When S2 and S5 are HIGH, a diode to VCC is integrated into the cir- cuit allowing for level shifting between 5V inputs and 3.3V outputs. Features s Undershoot protected to 2V (A and B Ports) s Voltage level shifting s 4 : switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Notes AN-5008 and AN-5021 for UHC details s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Applications Note Select pins S0, S1, S2, S3, S4 and S5 are intended to be used as static user configurable control pins. The AC per- formance of these pins has not been characterized or tested. Switching of these select pins during system opera- tion may temporarily disrupt output logic states and/or enable pin controls. 40-bit configuration can be achieved by connecting the OE1 and the OE6 pins to together. Ordering Code: Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. UHC® ¥ is a registered trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description FSTUD32450G (Note 1)(Note 2) BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide |
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Mô tả tương tự - FSTUD32450G |
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