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ADAU1442YSVZ-3A bảng dữ liệu(PDF) 3 Page - Analog Devices |
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ADAU1442YSVZ-3A bảng dữ liệu(HTML) 3 Page - Analog Devices |
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3 / 92 page  ADAU1442/ADAU1445/ADAU1446 Rev. C | Page 3 of 92 REVISION HISTORY 9/10—Rev. B to Rev. C Added Table 1, Renumbered Sequentially .....................................4 Changes to System Initialization Sequence Section ...................20 Changes to Table 12 ........................................................................24 Changes to Figure 20 ......................................................................29 Changes to EEPROM Format Section..........................................30 Changes to Table 26 ........................................................................39 Changes to Table 30 ........................................................................44 Changes to Stereo ASRC[3:0] Lock Status and Mute Register (Address 0xE101), Stereo ASRC[3:0] Mute Ramp Disable Register (Address 0xE103), and Stereo ASRC[7:4] Lock Status and Mute Register (Address 0xE141) Sections .......................58 Changes to Architecture Section and Figure 51..........................60 Changes to Core Run Register (Address 0xE228) Section ........61 Changes to Table 55 ........................................................................66 Changes to Table 59 ........................................................................67 Changes to Multipurpose Pins Section and Table 68 .................69 4/10—Rev. A to Rev. B Added ADAU1442 ............................................................. Universal Changes to General Description Section .......................................4 Changes to Table 1 ............................................................................5 Added Table 2; Renumbered Sequentially .....................................6 Changes to Table 4 ..........................................................................11 Changes to Overview Section........................................................16 Changes to Power-Up Sequence Section, System Initialization Sequence Section, and Table 6...................................................19 Changes to Data Bytes Section ......................................................28 Changes to Serial Clock Domains Section ..................................33 Changes to Flexible Audio Routing Matrix—Input Side Section.....47 Changes to ASRC Input Select Pairs[7:0] Registers (Address 0xE080 to Address 0xE087) Section ........................52 Changes to ASRC Output Rate Bits (Bits[5:0]) Section ..............54 Changes to Stereo ASRC[3:0] Lock Status and Mute Register (Address 0xE101) Section............................................................57 Changes to Stereo ASRC[7:4] Lock Status and Mute Register (Address 0xE141) Section..................................................................58 Changes to S/PDIF Transmitter Section ......................................64 Changes to Multipurpose Pins Section ........................................68 Added Multipurpose Pin Value Registers (Address 0x129A to Address 0x12A5) Section and Table 66; Renumbered Sequentially..................................................................................68 Change to Table 84..........................................................................82 Changes to Ordering Guide...................................................................91 4/09—Rev. 0 to Rev. A Added ADAU1446 ............................................................. Universal Added LQFP ....................................................................... Universal Added Minimum Digital Current (DVDD) of ADAU1446, Maximum Digital Current (DVDD) of ADAU1446, and AVDD, DVDD, PVDD During Operation of ADAU1446 Parameters, Table 1 .......................................................................5 Changes to Table 4 ............................................................................9 Changes to Overview Section........................................................16 Change to Table 9............................................................................21 Changes to Voltage Regulator Section .........................................23 Changes to EEPROM Format Section..........................................28 Changes to Serial Clock Domains Section ..................................32 Changes to Flexible Audio Routing Matrix—Input Side Section; Added Figure 40; Renumbered Sequentially...........................46 Changes to Stereo ASRC Routing Overview Section.................47 Changes to ASRC Input Select Pairs[7:0] Registers (Address 0xE080 to Address 0xE087) Section.......................................................51 Changes to ASRC Output Rate Bits (Bits[5:0]) Section.............53 Changes to Serial Output Data Selector Bits (Bits[5:0]) Section .......................................................................55 Changes to ASRC Modes and Settings Section...........................56 Added Table 43; Renumbered Sequentially.................................61 Updated Outline Dimensions........................................................90 Changes to Ordering Guide...........................................................90 1/09—Revision 0: Initial Version |
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