công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
AD7226KR bảng dữ liệu(PDF) 5 Page - Analog Devices |
|
AD7226KR bảng dữ liệu(HTML) 5 Page - Analog Devices |
5 / 16 page REV. AD7226 –5– CIRCUIT INFORMATION D/A SECTION The AD7226 contains four identical, 8-bit, voltage mode digital-to- analog converters. The output voltages from the converters have the same polarity as the reference voltage allowing single supply opera- tion. A novel DAC switch pair arrangement on the AD7226 allows a reference voltage range from 2 V to 12.5 V. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS, single-pole, double-throw switches. The simplified circuit diagram for one channel is shown in Figure 1. Note that VREF (Pin 4) and AGND (Pin 5) are common to all four DACs. RR R 2R 2R 2R 2R 2R DB0 DB5 DB6 DB7 VREF AGND SHOWN FOR ALL 1s ON DAC VOUT Figure 1. D/A Simplified Circuit Diagram The input impedance at the VREF pin of the AD7226 is the parallel combination of the four individual DAC reference input impedances. It is code dependent and can vary from 2 k W to infinity. The lowest input impedance (i.e., 2 KW) occurs when all four DACs are loaded with the digital code 01010101. Therefore, it is important that the reference presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 100 pF to 250 pF. Each VOUT pin can be considered as a digitally programmable voltage source with an output voltage of: VD V OUTX X REF = (1) where DX is fractional representation of the digital input code and can vary from 0 to 255/256. The source impedance is the output resistance of the buffer amplifier. OP AMP SECTION Each voltage-mode D/A converter output is buffered by a unity gain, noninverting CMOS amplifier. This buffer amplifier is capable of developing 10 V across a 2 k W load and can drive capacitive loads of 3300 pF. The output stage of this amplifier consists of a bipolar transistor from the VDD line and a current load to the VSS, the negative supply for the output amplifiers. This output stage is shown in Figure 2. The NPN transistor supplies the required output current drive (up to 5 mA). The current load consists of NMOS transistors which normally act as a constant current sink of 400 mA to VSS, giving each output a current sink capability of approximately 400 mA if required. The AD7226 can be operated single or dual supply resulting in different performance in some parameters from the output amplifiers. In single supply operation (VSS = 0 V = AGND), with the out- put approaching AGND (i.e., digital code approaching all 0s) VDD VSS I/P O/P 400 A Figure 2. Amplifier Output Stage the current load ceases to act as a current sink and begins to act as a resistive load of approximately 2 k W to AGND. This occurs as the NMOS transistors come out of saturation. This means that, in single supply operation, the sink capability of the ampli- fiers is reduced when the output voltage is at or near AGND. A typical plot of the variation of current sink capability with out- put voltage is shown in Figure 3. VOUT (V) 500 010 2 468 400 300 200 100 0 VSS = –5V VSS = 0 VDD = +15V Figure 3. Variation of ISINK with VOUT If the full sink capability is required with output voltages at or near AGND (= 0 V), then VSS can be brought below 0 V by 5 V and thereby maintain the 400 mA current sink as indicated in Figure 3. Biasing VSS below 0 V also gives additional headroom in the output amplifier which allows for better zero code error performance on each output. Also improved is the slew rate and negative-going settling time of the amplifiers (discussed later). Each amplifier offset is laser trimmed during manufacture to eliminate any requirement for offset nulling. DIGITAL SECTION The digital inputs of the AD7226 are both TTL and CMOS (5 V) compatible from VDD = 11.4 V to 16.5 V. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode from DGND to each MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible. 4 o f 1 4 D |
Số phần tương tự - AD7226KR |
|
Mô tả tương tự - AD7226KR |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |