IN0

IN7

MUX

T/H

ADC128S052

SCLK

AGND

DGND

CS

DIN

DOUT

CONTROL

LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

.

.

.

AGND

ADC128S052

SNAS333D – AUGUST 2005 – REVISED MARCH 2013

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Block Diagram

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

4 - 11

IN0 to IN7

DIGITAL I/O

Digital clock input. The guaranteed performance range of

16

SCLK

frequencies for this input is 3.2 MHz to 8 MHz. This clock directly

controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on

15

DOUT

the falling edges of the SCLK pin.

Digital data input. The ADC128S052's Control Register is loaded

14

DIN

through this pin on rising edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins.

1

CS

Conversions continue as long as CS is held low.

POWER SUPPLY

Positive analog supply pin. This voltage is also used as the

reference voltage. This pin should be connected to a quiet +2.7V to

2

+5.25V source and bypassed to GND with 1 µF and 0.1 µF

monolithic ceramic capacitors located within 1 cm of the power pin.

Positive digital supply pin. This pin should be connected to a +2.7V

13

capacitor located within 1 cm of the power pin.

3

AGND

The ground return for the analog supply and signals.

12

DGND

The ground return for the digital supply and signals.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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