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ADM9240ARU-REEL bảng dữ liệu(PDF) 7 Page - Analog Devices |
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ADM9240ARU-REEL bảng dữ liệu(HTML) 7 Page - Analog Devices |
7 / 22 page ADM9240 –7– REV. 0 SERIAL BUS INTERFACE Control of the ADM9240 is carried out via the serial bus. The ADM9240 is connected to this bus as a slave device, under the control of a master device, e.g., the PIIX4. The ADM9240 has a 7-bit serial bus address. When the device is powered up, it will do so with a default serial bus address. The five MSBs of the address are set to 01011, the two LSBs are determined by the logical states of Pin 1(NTEST_OUT/A0) and Pin 2 (A1) at power-up. These pins have internal 75 k Ω pull-down resistors, so if they are left open-circuit the default address will be 0101100. The facility to make hardwired changes to A1 and A0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one ADM9240 is used in a sys- tem. Once the ADM9240 has been powered up, the five MSBs of the serial bus address may be changed by writing a 7-bit word to the serial Address Pointer Register (the hardwired values of A0 and A1 cannot be overwritten). Thereafter, the new serial bus address must be used to select the ADM9240, until it is changed again, or the device is powered off. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/ W bit, which deter- mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowl- edge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/ W bit is a 0, the master will write to the slave device. If the R/ W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single READ or WRITE operation is limited only by what the master and slave devices can handle. 3. When all data bytes have been read or written, stop condi- tions are established. In WRITE mode, the master will pull the data line high during the tenth clock pulse to assert a STOP condition. In READ mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the case of the ADM9240, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions: To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the Address Pointer Register. This is illustrated in Figure 2a. The device address is sent over the bus followed by R/ W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register. R/ W 0 SCL SDA 1 0 1 1 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM9240 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE 19 1 ACK. BY ADM9240 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADM9240 STOP BY MASTER FRAME 3 DATA BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register |
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