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ADG663BRU bảng dữ liệu(PDF) 8 Page - Analog Devices

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ADG663BRU bảng dữ liệu(HTML) 8 Page - Analog Devices

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–8–
REV. 0
ADG661/ADG662/ADG663
SD
0.1 F
VDD
IN
VS
GND
VSS
RL
50
VOUT
0.1 F
VIN
VSS
VDD
7. Off Isolation
16-Lead TSSOP
(RU-16)
16
9
8
1
0.201 (5.10)
0.193 (4.90)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Test Circuits (Continued)
8. Channel-to-Channel Crosstalk
SD
0.1 F
VDD
VS
GND
VSS
50
NC
0.1 F
VIN1
VIN2
S
D
RL
50
VOUT
CHANNEL TO CHANNEL
CROSSTALK = 20
LOG VS/VOUT
VDD
VSS
APPLICATION
Figure 9 illustrates a precise, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an OP07. During the track mode, SW1 is closed and
the output VOUT follows the input signal VIN. In the hold mode,
SW1 is opened and the signal is held by the hold capacitor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG661/ADG662/
ADG663 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 15
µV/µs.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. This compensation network also re-
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the
±3 V input
range. The acquisition time is 2.5 ms while the settling time is
1.85
µs.
+5V
–5V
2200pF
RC
75
CC
1000pF
CH
2200pF
VOUT
ADG661
ADG662
ADG663
SW2
SW1
S
S
D
D
+5V
–5V
AD845
+5V
–5V
VIN
OP07
Figure 9. Accurate Sample-and-Hold


Số phần tương tự - ADG663BRU

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Analog Devices
ADG663BRU AD-ADG663BRU Datasheet
123Kb / 8P
   LC2MOS Precision 5 V Quad SPST Switches
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