AD7836

–9–

REV. A

Power-On with CLR Low

The output stage of the AD7836 has been designed to allow

output stability during power-on. If CLR is kept low during

power-on, then just after power is applied to the AD7836, the

DAC

6k

DUTGND

R

R

Ω resistor. This thin-film resistor is connected in

parallel with the gain resistors of the output amplifier. The out-

amplifier’s output is thus at the same voltage as the DUTGND

pin. The output stage remains configured as in Figure 14 until

±10 V. By

now the output amplifier has enough headroom to handle sig-

nals at its input and has also had time to settle. The internal

situation is shown in Figure 15. Now the output amplifier is

DUTGND voltage is still connected to the noninverting input

DAC

6k

DUTGND

R

R

via the configuration shown in Figure 15.

When CLR is taken back high, the output stage is configured as

gain of two configuration. The voltage that appears on the Vout

pins is determined by the data present in the DAC registers. To

set all output voltages to the same known state, a write to

DATA REG E with the SEL pin high allows all DAC registers

to be updated with the same data.

DAC

6k

DUTGND

R

R

Figure 16. Output Stage After CLR Is Taken High

Power-On with CLR High

If CLR is high on the application of power to the device, the

output stages of the AD7836 are configured as in Figure 17

thereby connecting the output of the DAC to the input of its

open thus connecting the output amplifier as a unity gain

Ω

±10 V.

DAC

6k

DUTGND

R

R

Figure 17. Output Stage Powering Up with CLR High

±10 V

When the supplies reach

±10 V, the internal power on circuitry

stage as shown in Figure 18.

DAC

6k

DUTGND

R

R

Figure 18. Output Stage Powering Up with CLR High

±10 V