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AD5201BRMZ50 bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD5201BRMZ50 bảng dữ liệu(HTML) 3 Page - Analog Devices |
3 / 15 page –3– AD5200/AD5201 (VDD = 5 V 10%, or 3 V 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C unless otherwise noted.) AD5201 ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ 1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 R-DNL RWB, VA = No Connect –0.5 ± 0.05 +0.5 LSB Resistor Integral Nonlinearity 2 R-INL RWB, VA = No Connect –1 ± 0.1 +1 LSB Nominal Resistor Tolerance 3 ∆R AB TA = 25 °C –30 +30 % Resistance Temperature Coefficient RAB/ ∆TV AB = V DD, Wiper = No Connect 500 ppm/ °C Wiper Resistance RW VDD = 5 V 50 100 Ω DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution 4 N 6 Bits Differential Nonlinearity 5 DNL –0.5 ± 0.01 +0.5 LSB Integral Nonlinearity 5 INL –1 ± 0.02 +1 LSB Voltage Divider Temperature Coefficient ∆V W/ ∆T Code = 10 H 5 ppm/ °C Full-Scale Error VWFSE Code = 20 H –1/2 –1/4 0 LSB Zero-Scale Error VWZSE Code = 00 H 0 +1/4 +1/2 LSB RESISTOR TERMINALS Voltage Range 6 VA, B, W VSS VDD V Capacitance 7 A, B CA, B f = 1 MHz, Measured to GND, Code = 10 H 45 pF Capacitance 7 WC W f = 1 MHz, Measured to GND, Code = 10 H 60 pF Shutdown Supply Current 8 IDD_SD VDD = 5.5 V 0.01 5 µA Common-Mode Leakage ICM VA = VB = VDD/2 1 nA DIGITAL INPUTS AND OUTPUTS Input Logic High VIH 2.4 V Input Logic Low VIL 0.8 V Input Logic High VIH VDD = 3 V, VSS = 0 V 2.1 V Input Logic Low VIL VDD = 3 V, VSS = 0 V 0.6 V Input Current IIL VIN = 0 V or 5 V ±1 µA Input Capacitance 7 CIL 5pF POWER SUPPLIES Logic Supply VLOGIC 2.7 5.5 V Power Single-Supply Range VDD RANGE VSS = 0 V –0.3 5.5 V Power Dual-Supply Range VDD/SS RANGE ± 2.3 ± 2.7 V Positive Supply Current IDD VIH = +5 V or VIL = 0 V 15 40 µA Negative Supply Current ISS VSS = –5 V 15 40 µA Power Dissipation 9 PDISS VIH = +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V 0.2 mW Power Supply Sensitivity PSS ∆V DD = +5 V ± 10% –0.01 0.001 +0.01 %/% DYNAMIC CHARACTERISTICS 7, 10 Bandwidth –3 dB BW_10 k Ω RAB = 10 k Ω, Code = 10 H 600 kHz BW_50 k Ω RAB = 50 k Ω, Code = 10 H 100 kHz Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz, R AB = 10 k Ω 0.003 % VW Settling Time (10 k Ω/50 kΩ)t S VA = 5 V, VB = 0 V, ± 1 LSB Error Band 2/9 µs Resistor Noise Voltage Density eN_WB RWB = 5 k Ω, RS = 0 9 nV √Hz NOTES 1Typicals represent average readings at 25 °C and VDD = 5 V, VSS = 0 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W = VDD/R for both VDD = +2.7 V, VSS = –2.7 V. 3 V AB = VDD, Wiper (VW) = No connect. 4 Six bits are needed for 33 positions even though it is not a 64-position device. 5 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. 6 Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 7 Guaranteed by design and not subject to production test. 8 Measured at the A terminal. A terminal is open-circuited in shutdown mode. 9 P DISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use V DD = 5 V, VSS = 0 V. Specifications subject to change without notice. REV. D |
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