5

8735A–SEEPR–1/11

Atmel AT93C56B/66B

Table 1-4.

Instruction Set for the Atmel AT93C56B and Atmel AT93C66B

Note:

The Xs in the address field represent “don’t care” values, and must be clocked

2.

Functional Description

The Atmel

operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of

CS, and consists of a start bit (logic one) followed by the appropriate op code and the desired memory address location.

READ (READ): The read (READ) instruction contains the address code for the memory location to be read. After the

instruction and address are decoded, data from the selected memory location is available at the serial output pin, DO.

Output data changes are synchronized with the rising edges ofthe serial clock, SK. It should be noted that a dummy bit

(logic zero) precedes the 8- or 16-bit data output string. The AT93C56B/66B supports sequential read operations. The

device will automatically increment the internal address pointer and clock out the next memory location as long as chip

select (CS) is held high. In this case, the dummy bit (logic zero) will not be clocked out between memory locations, thus

allowing for a continuous stream of data to be read.

ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the erase/write disable

(EWDS) state when power is first applied. An erase/write enable (EWEN) instruction must be executed first before any

programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until

an EWDS instruction is executed or V

ERASE (ERASE): The erase (ERASE) instruction programs all bits in the specified memory location to the logical-one

state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the

ready/busy status of the part if CS is brought high after being kept low for a minimum of 250ns (t

indicates that the selected memory location has been erased and the part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8- or 16-bits of data to be written into the specified memory

location. The self-timed programming cycle, t

pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of 250ns (t

logic zero at DO indicates that programming is still in progress. A logic one indicates that the memory location at the

specified address has been written with the data pattern contained in the instruction and the part is ready for further

instructions. A ready/busy status cannot be obtained if CS is brought high after the end of the self-timed programming

cycle, t

ERASE ALL (ERAL): The erase all (ERAL) instruction programs every bit in the memory array to the logic one state, and

is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being

kept low for a minimum of 250ns (t

Instruction

SB

Op

Code

Address

Data

Comments

x 8

x 16

x 8

x 16

READ

1

10

A

A

Reads data stored in memory at specified address

EWEN

1

00

11XXXXXXX

11XXXXXX

Write enable must precede all programming modes

ERASE

1

11

A

A

Erases memory location A

WRITE

1

01

A

A

D

D

Writes memory location A

ERAL

1

00

10XXXXXXX

10XXXXXX

Erases all memory locations. Valid only at

V

WRAL

1

00

01XXXXXXX

01XXXXXX

D

D

Writes all memory locations. Valid only at

V

EWDS

1

00

00XXXXXXX

00XXXXXX

Disables all programming instructions