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ADS7817UCG4 bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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ADS7817UCG4 bảng dữ liệu(HTML) 9 Page - Texas Instruments |
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9 / 21 page  ADS7817 9 SBAS066A In each case, care should be taken to ensure that the output impedance of the sources driving the +In and –In inputs are matched. If this is not observed, the two inputs could have different settling times. This may result in offset error, gain error, and linearity error which change with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS7817 more acquisi- tion time. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS7817 charges the inter- nal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (15pF) to a 12-bit settling level within 1.5 clock cycles. When the converter goes into the hold mode or while it is in the power down mode, the input impedance is greater than 1G Ω. Care must be taken regarding the absolute analog input voltage. The +In input should always remain within the range of GND –300mV to VCC +300mV. The –In input should always remain within the range of GND –300mV to 4V. Outside of these ranges, the converter’s linearity may not meet specifications. REFERENCE INPUT The external reference sets the analog input range. The ADS7817 will operate with a reference in the range of 100mV to 2.5V. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to two times the reference voltage divided by 4096. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The typical performance curves of “Change in Offset vs Reference Voltage” and “Change in Gain vs Reference Voltage” provide more infor- mation. The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5V reference, the internal noise of the converter typically contributes only 0.52 LSB peak-to-peak of potential error to the output code. When the external reference is 100mV, the potential error contribution from the internal noise will be 25 times larger— 13 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conver- sion results. For more information regarding noise, consult the typical performance curves “Effective Number of Bits vs Reference Voltage” and “Peak-to-Peak Noise vs Reference Voltage.” Note that the effective number of bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distor- tion) with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 • ENOB + 1.76. With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter will also be more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. The current that must be provided by the external reference will depend on the conversion result. The current is lowest at negative full-scale (800h) and is typically 15 µA at a 200kHz conversion rate (25 °C). For the same conditions, the current will increase as the analog input approaches positive full scale, reaching 25 µA at an output result of 7FFh. The current does not increase linearly, but depends, to some degree, on the bit pattern of the digital output. The reference current diminishes directly with both conver- sion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the con- verter more quickly during a given conversion period will not reduce the overall current drain from the reference. The reference current changes only slightly with temperature. See the curves, “Reference Current vs Sample Rate” and “Reference Current vs Temperature” in the Typical Perfor- mance Curves section for more information. DIGITAL INTERFACE SERIAL INTERFACE The ADS7817 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface as shown in Figure 4 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmit- ted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. TABLE I. Timing Specifications –40 °C to +85°C. SYMBOL DESCRIPTION MIN TYP MAX UNITS tSMPL Analog Input Sample TIme 1.5 2.0 Clk Cycles tCONV Conversion Time 12 Clk Cycles tCYC Throughput Rate 200 kHz tCSD CS Falling to 0 ns DCLOCK LOW tSUCS CS Falling to 30 ns DCLOCK Rising thDO DCLOCK Falling to 15 ns Current DOUT Not Valid tdDO DCLOCK Falling to Next 85 150 ns DOUT Valid tdis CS Rising to DOUT Tri-State 25 50 ns ten DCLOCK Falling to DOUT 50 100 ns Enabled tf DOUT Fall Time 70 100 ns tr DOUT Rise Time 60 100 ns |
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