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ADS7817PB bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS7817PB bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 21 page ADS7817 8 SBAS066A THEORY OF OPERATION The ADS7817 is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6 µ CMOS process. The architecture and process allow the ADS7817 to acquire and convert an analog signal at up to 200,000 conversions per second while consuming very little power. The ADS7817 requires an external reference, an external clock, and a single +5V power source. The external refer- ence can be any voltage between 100mV and 2.5V. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS7817. The external clock can vary between 10kHz (625Hz through- put) and 3.2MHz (200kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 150ns. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS7817. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS7817 after the conversion is complete and to obtain the serial data least significant bit first. See the Digital Interface section for more information. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS7817: single-ended or differential (see Figure 1). When the input is single-ended, the –In input is held at a fixed voltage. The +In input swings around the same voltage and the peak-to-peak amplitude is 2 • VREF. The value of VREF determines the range over which the common voltage may vary (see Figure 2). When the input is differential, the amplitude of the input is the difference between the +In and –In input, or: +In – (–In). A voltage or signal is common to both of these inputs. The peak- to-peak amplitude of each input is VREF about this common voltage. However, since the inputs are 180 ° out of phase, the peak-to-peak amplitude of the difference voltage is 2 • VREF. The value of VREF also determines the range of the voltage that may be common to both inputs (see Figure 3). FIGURE 1. Methods of Driving the ADS7817: Single- Ended or Differential. FIGURE 2. Single-Ended Input: Common Voltage Range vs VREF. FIGURE 3. Differential Input: Common Voltage Range vs VREF. ADS7817 ADS7817 Single-Ended Input Common Voltage 2 • V REF peak-to-peak Differential Input Common Voltage V REF peak-to-peak V REF peak-to-peak 0.0 0.5 1.0 1.5 2.0 2.5 V REF (V) –1 0 1 2 3 4 5 2.8 2.2 –0.3 4.0 V CC = 5V Single-Ended Input 0.0 0.5 1.0 1.5 2.0 2.5 V REF (V) 2.75 V CC = 5V 1.95 4.0 –0.3 –1 0 1 2 3 4 5 Differential Input |
Số phần tương tự - ADS7817PB |
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Mô tả tương tự - ADS7817PB |
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