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ADC0804LCWMX bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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ADC0804LCWMX bảng dữ liệu(HTML) 4 Page - Texas Instruments |
4 / 48 page ADC0801, ADC0802 ADC0803, ADC0804, ADC0805 SNOSBI1B – NOVEMBER 2009 – REVISED FEBRUARY 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS The following specifications apply for VCC=5 VDC and TMIN≤ TA≤TMAX (unless otherwise specified) PARAMETER CONDITIONS MIN TYP MAX UNITS fCLK = 640 kHz (1) 103 114 µs TC Conversion Time See (2)(1) 66 73 1/fCLK Clock Frequency 100 640 1460 kHz fCLK VCC = 5V (2) Clock Duty Cycle 40% 60% INTR tied to WR with CS = 0 VDC, CR Conversion Rate in Free-Running Mode 8770 9708 conv/s fCLK = 640 kHz tW(WR)L Width of WR Input (Start Pulse Width) CS = 0 VDC (3) 100 ns Access Time (Delay from Falling Edge of RD tACC CL = 100 pF 135 200 ns to Output Data Valid) TRI-STATE Control (Delay from Rising Edge of CL = 10 pF, RL = 10k (See TRI-STATE t1H, t0H 125 200 ns RD to Hi-Z State) TEST CIRCUITS AND WAVEFORMS) Delay from Falling Edge of WR or RD to Reset tWI, tRI 300 450 ns of INTR CIN Input Capacitance of Logic Control Inputs 5 7.5 pF COUT TRI-STATE Output Capacitance (Data Buffers) 5 7.5 pF CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately] VIN (1) Logical “1” Input Voltage (Except Pin 4 CLK IN) VCC = 5.25 VDC 2 15 VDC VIN (0) Logical “0” Input Voltage (Except Pin 4 CLK IN) VCC = 4.75 VDC 0.8 VDC IIN (1) Logical “1” Input Current (All Inputs) VIN = 5 VDC 0.005 1 µADC IIN (0) Logical “0” Input Current (All Inputs) VIN = 0 VDC –1 –0.005 µADC CLOCK IN AND CLOCK R CLK IN (Pin 4) Positive Going Threshold VT+ 2.7 3.1 3.5 VDC Voltage CLK IN (Pin 4) Negative Going Threshold VT− 1.5 1.8 2.1 VDC Voltage VH CLK IN (Pin 4) Hysteresis (VT+)–(VT−) 0.6 1.3 2 VDC VOUT (0) Logical “0” CLK R Output Voltage IO = 360 µA, VCC = 4.75 VDC 0.4 VDC VOUT (1) Logical “1” CLK R Output Voltage IO = −360 µA, VCC = 4.75 VDC 2.4 VDC DATA OUTPUTS AND INTR Logical “0” Output Voltage VOUT (0) Data Outputs IOUT = 1.6 mA, VCC = 4.75 VDC 0.4 VDC INTR Output IOUT = 1.0 mA, VCC = 4.75 VDC 0.4 VDC IO = −360 µA, VCC = 4.75 VDC 2.4 VDC VOUT (1) Logical “1” Output Voltage IO = −10 µA, VCC = 4.75 VDC 4.5 VDC VOUT = 0 VDC –3 µADC TRI-STATE Disabled Output Leakage (All Data IOUT Buffers) VOUT = 5 VDC 3 µADC ISOURCE VOUT Short to GND, TA = 2 5°C 4.5 6 mADC ISINK VOUT Short to VCC, TA = 25°C 9 16 mADC POWER SUPPLY Supply Current (Includes Ladder Current) fCLK = 640 kHz, VREF/2 = NC, ICC ADC0801/02/03/04LCJ/05 1.1 1.8 mA TA = 25°C and CS = 5 V ADC0804LCN/LCWM 1.9 2.5 mA (1) Accuracy is specified at fCLK = 640 kHz. At higher clock frequencies accuracy can degrade. For lower clock frequencies, the duty cycle limits can be extended so long as the minimum clock high time interval or minimum clock low time interval is no less than 275 ns. (2) With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The start request is internally latched, see Figure 48 and FUNCTIONAL DESCRIPTION. (3) The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see TIMING DIAGRAMS). 4 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated Product Folder Links: ADC0801, ADC0802 ADC0803, ADC0804, ADC0805 |
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