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SN54ABT162841, SN74ABT162841
20BIT BUSINTERFACE DTYPE LATCHES
WITH 3STATE OUTPUTS
SCBS665C − JUNE 1996 − REVISED JUNE 2004
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The outputs, which are designed to sink up to 12 mA, include equivalent 25-
Ω series resistors to reduce
overshoot and undershoot.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
HL
L
L
LX
Q0
H
X
X
Z


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