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AD5243BRMZ50-RL7 bảng dữ liệu(PDF) 5 Page - Analog Devices

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Data Sheet
AD5243/AD5248
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS: ALL VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency
fSCL
0
400
kHz
Bus-Free Time Between Stop and Start, tBUF
t1
1.3
μs
Hold Time (Repeated Start), tHD;STA
t2
After this period, the first clock pulse is
generated.
0.6
μs
Low Period of SCL Clock, tLOW
t3
1.3
μs
High Period of SCL Clock, tHIGH
t4
0.6
μs
Setup Time for Repeated Start Condition, tSU;STA
t5
0.6
μs
Data Hold Time, tHD;DAT2
t6
0.9
μs
Data Setup Time, tSU;DAT
t7
100
ns
Fall Time of Both SDA and SCL Signals, tF
t8
300
ns
Rise Time of Both SDA and SCL Signals, tR
t9
300
ns
Setup Time for Stop Condition, tSU;STO
t10
0.6
μs
1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 45 to Figure 48).
2 The maximum tHD:DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
t1
t2
t3
t8
t8
t9
t9
t6
t4
t7
t5
t2
t10
PS
S
SCL
SDA
P
Figure 3. I2C Interface Detailed Timing Diagram


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