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74HCT74PW bảng dữ liệu(PDF) 1 Page - NXP Semiconductors |
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74HCT74PW bảng dữ liệu(HTML) 1 Page - NXP Semiconductors |
1 / 21 page 1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Input levels: For 74HC74: CMOS level For 74HCT74: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 Cto+85 C and from 40 Cto+125 C 3. Ordering information 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger Rev. 4 — 27 August 2012 Product data sheet Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC74N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HCT74N 74HC74D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HCT74D 74HC74DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HCT74DB |
Số phần tương tự - 74HCT74PW |
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Mô tả tương tự - 74HCT74PW |
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