www.fairchildsemi.com

REV. 1.1.1 3/19/01

Features

• Slope, height, and bandwidth adjustable

• Optimized group delays (500 Hz to 6.4 kHz)

• On chip anti-alias filter

• Bypass mode

• Low supply current 6 mA typical from ±5V supplies

• TTL / CMOS compatible interface

• Double buffered data latch

• Selectable master clock 1.544 or 1.536 MHz

• Synchronous or asynchronous data loading capability

• Compatible with ML2003 and ML2004 logarithmic

gain/attenuator

General Description

The ML2021 is a monolithic analog line equalizer for tele-

phone applications. The ML2021 consists of a switched

capacitor filter that realizes a family of frequency response

curves optimized for telephone line equalization while mini-

mizing group delay.

The ML2021 consists of a continuous anti-aliasing filter,

three programmable switched capacitor equalization filters,

an output smoothing filter, a 600

Ω driver, and a digital

section for the serial interface.

The equalization filters adjust the slope, height, and band-

width of the frequency response. The desired frequency

response is programmed by a digital 14-bit serial input data

stream.

Block Diagram

Pin Connections

CLKSEL

AGND

CLKSEL

SID

NC

LATO

SCK

NC

SOD

CLK

CLKSEL

SID

NC

LATO

SCK

NC

SOD

CLK

AGND

AGND

LATI

LATI

NC

NC

GND

GND

TOP VIEW

TOP VIEW

1

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLK

CLOCK

GENERATOR

SMOOTHING

FILTER

MUX

ANTIALIAS

LO PASS

SLOPE

SECTION

HEIGHT

SECTION

BANDPASS

SECTION

LATI

SID

GND

SOD

SCK

LATO

1

54

4

14

14-BIT LATCH

14-BIT SHIFT REGISTER

ML2021

16-PIN DIP

ML2021

18-PIN SOIC

ML2021

Telephone Line Equalizer