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ADM800MARN bảng dữ liệu(PDF) 8 Page - Analog Devices |
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8 / 12 page ADM691A/ADM693A/ADM800L/M –8– REV. 0 Changing the Watchdog and Reset Timeout The watchdog and reset timeout periods may be controlled us- ing OSC SEL and OSC IN. Please refer to Table II. With both these inputs floating (or connected to VOUT) as in Figure 16, the reset timeout is fixed at 200 ms and the watchdog timeout is fixed at 1.6 sec.. If OSC IN is connected to GND as in Figure 16, the reset timeout period remains at 200 ms but a short (100 ms) watchdog timeout period is selected (except immedi- ately following a reset where it reverts to 1.6 sec). By connecting OSC SEL to GND it is possible to select alternative timeout pe- riods by either connecting a capacitor from OSC IN to GND or by overdriving OSC IN with an external clock. With an external capacitor, the watchdog timeout period is Twd (ms) = 600 (C/47 pF) and the reset active period is Treset (ms) = 1200 (C/47 pF) With an external clock connected to OSC IN, the timeout periods become Twd = 1024 (1/fCLK) Treset = 2048 (1/fCLK) Battery-Switchover Section During normal operation with VCC higher than the reset thresh- old and higher than VBATT, VCC is internally switched to VOUT via an internal PMOS transistor switch. This switch has a typi- cal on-resistance of 0.75 Ω and can supply up to 250 mA at the VOUT terminal. VOUT is normally used to drive a RAM memory bank which may require instantaneous currents of greater than 250 mA. If this is the case then a bypass capacitor should be connected to VOUT. The capacitor will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used. If the continuous output current requirement at VOUT exceeds 250 mA or if a lower VCC–VOUT voltage differential is desired, an external PNP pass transistor may be connected in parallel with the internal transistor. The BATT ON output can drive the base of the external transistor. If VCC drops below VBATT and below the reset threshold, battery backup is selected. A 7 Ω MOSFET switch connects the V BATT input to VOUT. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels required for battery backup of CMOS RAM or other low power CMOS cir- cuitry. The supply current in battery backup is typically 0.04 µA. High value capacitors, either standard electrolytic or the farad- size double layer capacitors, can also be used for short-term memory backup. If the battery-switchover section is not used, VBATT should be connected to GND and VOUT should be connected to VCC. When VCC is below the reset threshold, the watchdog function is disabled and WDI goes high impedance as it is disconnected from its internal resistor network. The internal oscillator is enabled when OSC SEL is high or floating. In this mode, OSC IN selects between the 1.6 second and 100 ms watchdog timeout periods. CEIN RESET RESET VCC CEOUT OSC SEL RESET THRESHOLD 80µs t RS 12µs t RS 80µs Figure 17. RESET and Chip Enable Timing OSC SEL OSC IN 7 8 ADM69_A ADM800_ CLOCK 0 TO 250kHz Figure 18a. External Clock Source OSC SEL OSC IN 7 8 ADM69_A ADM800_ NC NC Figure 18b. Internal Oscillator (1.6 s Watchdog) 7 OSC SEL OSC IN 8 ADM69_A ADM800_ COSC Figure 18c. External Capacitor Table II. Reset Pulse Width and Watchdog Timeout Selections Watchdog Timeout Period OSC SEL OSC IN Normal Immediately After Reset Reset Active Period Low External Clock Input 1024 clks 4096 clks 2048 clks Low External Capacitor 600 ms × C/47 pF 2.4 s × C/47 pF 1200 ms × C/47 pF Floating Low 100 ms 1.6 s 200 ms Floating Floating or VOUT 1.6 s 1.6 s 200 ms |
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