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FW21555AA bảng dữ liệu(PDF) 6 Page - Intel Corporation |
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FW21555AA bảng dữ liệu(HTML) 6 Page - Intel Corporation |
6 / 6 page 21555AA/BA and 21555AB/BB Differences 6 Application Note 4.0 BSDL Data Being Driven Late The 21555AA/BA BSDL (Boundary-Scan Description Language) data was being driven one clock cycle late causing a potential device contention issue if BSDL was single stepped during testing. This behavior has been corrected in the 21555AB/BB device. The BSDL file does not change. 5.0 New Feature - PCI 2.3 Compliance The PCI Special Interest Group ratified the PCI 2.3 specification requiring an additional bit in the control register and an additional bit in the status register. The new register bits are as follows: Note: Please refer to the following documentation for more information: • 21555 Non-transparent PCI-to-PCI Bridge Datasheet • 21555 Non-transparent PCI-to-PCI Bridge User’s Manual • 21555 Non-transparent PCI-to-PCI Bridge Hardware Implementation manual • 21555 Specification Update Table 1. Primary and Secondary Command Registers Bit Name R/W Description 10 Interrupt Disable Bit R/W This bit disables the 21555 from asserting p_inta_l / s_inta_l. • When 0, enables the 21555 to assert its p_inta_l / s_inta_l signal. • When 1, disables the 21555 ability to assert the p_inta_l / s_inta_l signal. This bit’s state after RST# is 0. Offsets Primary Command Secondary Command Primary byte 05:04h 45:44h Secondary byte 45:44h 05:04h Table 2. Primary and Secondary Status Registers Bit Name R/W Description 3 Interrupt Status Bit R This bit reflects the state of the interrupt in the 21555 bridge. • Only when the Interrupt Disable Bit in the command register is set to 0 and the appropriate interrupt status bit set to 1 will the p_inta_l/s_inta_l signals be asserted. • Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Offsets Primary Status Secondary Status Primary byte 07:06h 47:46h Secondary byte 47:46h 07:06h |
Số phần tương tự - FW21555AA |
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Mô tả tương tự - FW21555AA |
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