công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

ADR421 bảng dữ liệu(PDF) 10 Page - Analog Devices

tên linh kiện ADR421
Giải thích chi tiết về linh kiện  Dual, Current-Output, Serial-Input, 16-/14-Bit DACs
Download  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

ADR421 bảng dữ liệu(HTML) 10 Page - Analog Devices

Back Button ADR421 Datasheet HTML 6Page - Analog Devices ADR421 Datasheet HTML 7Page - Analog Devices ADR421 Datasheet HTML 8Page - Analog Devices ADR421 Datasheet HTML 9Page - Analog Devices ADR421 Datasheet HTML 10Page - Analog Devices ADR421 Datasheet HTML 11Page - Analog Devices ADR421 Datasheet HTML 12Page - Analog Devices ADR421 Datasheet HTML 13Page - Analog Devices ADR421 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 24 page
background image
AD5545/AD5555
Data Sheet
Rev. G | Page 10 of 24
SERIAL DATA INTERFACE
The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK)
serial data interface for single channel update operation. With
Table 7 as an example (AD5545), users can tie LDAC low
and RS high, and then pull CS low for an 18-bit duration. New
serial data is then clocked into the serial-input register in an 18-
bit data-word format with the MSB bit loaded first. Table 8
defines the truth table for the AD5555. Data is placed on the
SDI pin and clocked into the register on the positive clock edge
of CLK. For the AD5545, only the last 18-bits clocked into the
serial register are interrogated when the CS pin is strobed high,
transferring the serial register data to the DAC register and
updating the output. If the applied microcontroller outputs
serial data in different lengths than the AD5545, such as 8-bit
bytes, three right justified data bytes can be written to the
AD5545. The AD5545 ignores the six MSB and recognizes the
18 LSB as valid data. After loading the serial register, the rising
edge of CS transfers the serial register data to the DAC register
and updates the output; during the CS strobe, the CLK should
not be toggled.
If users want to program each channel separately but update them
simultaneously, program LDAC and RS high initially, then
pull CS low for an 18-bit duration and program DAC A with the
proper address and data bits. CS is then pulled high to latch data
to the DAC A register. At this time, the output is not updated. To
load DAC B data, pull CS low for an 18-bit duration and program
DAC B with the proper address and data, then pull CS high to
latch data to the DAC B register. Finally, pull LDAC low and then
high to update both the DAC A and DAC B outputs
simultaneously.
Table 6 shows that each DAC A and DAC B can be individually
loaded with a new data value. In addition, a common new data
value can be loaded into both DACs simultaneously by setting Bit
A1 = A0 = high. This command enables the parallel combination
of both DACs, with IOUTA and IOUTB tied together, to act as one
DAC with significant improved noise performance.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to digital ground (DGND) and VDD as shown in
Figure 19.
VDD
02918- 0- 007
5k
DGND
DIGITAL
INPUTS
Figure 19. Equivalent ESD Protection Circuits
Table 4. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
Note that only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D15 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 5. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format1
MSB
LSB
Bit Position
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
Note that only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bit D13 to Bit D0) to the
decoded DAC input register address determined by Bit A1 and Bit A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in
are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 6. Address Decode
A1
A0
DAC Decoded
0
0
None
0
1
DAC A
1
0
DAC B
1
1
DAC A and DAC B


Số phần tương tự - ADR421

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Analog Devices
ADR421 AD-ADR421 Datasheet
223Kb / 16P
   Ultraprecision Low Noise, 2.048 V/2.500 V/ 3.00 V/5.00 V XFET Voltage References
REV. B
ADR421 AD-ADR421 Datasheet
247Kb / 5P
   Software-Calibrated, 1 MHz to 8 GHz, 60 dB RF Power Measurement System Using a Logarithmic Detector
REV. C
ADR421 AD-ADR421 Datasheet
1Mb / 20P
   Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with Four-Quadrant Resistors
REV. D
ADR421 AD-ADR421 Datasheet
3Mb / 21P
   Precision, Micropower, High Current Output Voltage Reference
Rev. 0
ADR421 AD-ADR421 Datasheet
3Mb / 26P
   Precision, Micropower, High Current Output Voltage References
Rev. A
More results

Mô tả tương tự - ADR421

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Analog Devices
AD5545 AD-AD5545_16 Datasheet
977Kb / 23P
   Dual, Current-Output, Serial-Input, 16-/14-Bit DACs
AD5543 AD-AD5543_15 Datasheet
582Kb / 20P
   Current Output/Serial Input, 16-/14-Bit DACs
Rev. F
AD5553 AD-AD5553_15 Datasheet
582Kb / 20P
   Current Output/Serial Input, 16-/14-Bit DACs
Rev. F
AD5543 AD-AD5543_12 Datasheet
582Kb / 20P
   Current Output/Serial Input, 16-/14-Bit DACs
Rev. F
AD5544 AD-AD5544_12 Datasheet
694Kb / 24P
   Quad, Current-Output, Serial-Input 16-/14-Bit DACs
Rev. G
AD5544ARSZ AD-AD5544ARSZ Datasheet
875Kb / 28P
   Quad, Current-Output, Serial-Input 16-/14-Bit DACs
REV. F
AD5544 AD-AD5544_13 Datasheet
735Kb / 24P
   Quad, Current-Output, Serial-Input 16-/14-Bit DACs
Rev. G
AD5544 AD-AD5544_04 Datasheet
909Kb / 20P
   Quad, Current-Output, Serial-Input 16-/14-Bit DACs
REV. A
AD5544 AD-AD5544_15 Datasheet
747Kb / 24P
   Quad, Current-Output, Serial-Input 16-/14-Bit DACs
AD5544 AD-AD5544 Datasheet
473Kb / 16P
   Quad, Current-Output Serial-Input, 16-Bit/14-Bit DACs
REV. 0
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com