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AD7091RBRMZ bảng dữ liệu(PDF) 5 Page - Analog Devices

tên linh kiện AD7091RBRMZ
Giải thích chi tiết về linh kiện  1 MSPS, Ultralow Power, 12-Bit ADC in 10-Lead LFCSP and MSOP
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Data Sheet
AD7091R
Rev. 0 | Page 5 of 20
TIMING SPECIFICATIONS
VDD = 2.75 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted.1
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
50
MHz max
Frequency of serial read clock
t1
8
ns max
Delay from the end of a conversion until SDO three-state is disabled
t2
7
ns max
Data access time after SCLK falling edge
t3
0.4 tSCLK
ns min
SCLK high pulse width
t4
3
ns min
SCLK to data valid hold time
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
15
ns max
SCLK falling edge to SDO high impedance
t7
10
ns min
CONVST pulse width
t8
650
ns max
Conversion time
t9
6
ns min
CS low time before the end of a conversion
t10
18
ns max
Delay from
CS until SDO three-state is disabled
t11
8
ns min
CS high time before the end of a conversion
t12
8
ns min
Delay from the end of a conversion until
CS falling edge
t13
50
ms typ
Power-up time with internal reference2
100
µs max
Power-up time with external reference
tQUIET
50
ns min
Time between last SCLK edge and next CONVST pulse
1
Sample tested during initial release to ensure compliance.
2
With a 2.2 µF reference capacitor.


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